公开(公告)号：KR1020100055863A

公开(公告)日：2010-05-27

申请号：KR1020080114749

申请日：2008-11-18

Applicant: 삼성전자주식회사

Inventor： 지정근 ,  박정현 ,  형용우 ,  손호민 ,  이웅 ,  함희영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/02057 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/31051 ,  H01L21/76224

Abstract: PURPOSE: A method for manufacturing a nonvolatile memory is provided to improve a threshold voltage distribution of a cell transistor by forming a thicker tunneling oxidation layer on the edge than the center on an active region. CONSTITUTION: An active region(105) is limited by forming a trench by etching a part of a substrate. The edge of the active region is exposed from a buffer layer. A device isolation layer(160) is formed to cover the exposed edge of the active region in the trench. The edge of the active region is exposed by removing a hard mask and a pad oxidation layer. A first insulation layer is formed on the exposed edge of the active region. A second insulation layer is formed on the expose upper side of the active region. The second insulation layer is thinner than the first insulation layer. A conductive pattern is formed on the first and second insulation layers.

Abstract translation: 目的：提供一种用于制造非易失性存储器的方法，以通过在边缘上形成比活性区域上的中心更厚的隧道氧化层来改善单元晶体管的阈值电压分布。 构成：通过蚀刻衬底的一部分来形成沟槽来限制有源区（105）。 有源区域的边缘从缓冲层露出。 形成器件隔离层（160）以覆盖沟槽中有源区域的暴露边缘。 通过去除硬掩模和焊盘氧化层来暴露有源区域的边缘。 第一绝缘层形成在有源区的暴露边缘上。 在活性区域的暴露上侧形成第二绝缘层。 第二绝缘层比第一绝缘层薄。 导电图案形成在第一和第二绝缘层上。