公开(公告)号：KR1020090001383A

公开(公告)日：2009-01-08

申请号：KR1020070065720

申请日：2007-06-29

Applicant: 삼성전자주식회사

Inventor： 장규백 ,  김성진 ,  홍성덕 ,  변현숙

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/04

CPC classification number: H01L28/91 ,  H01L27/10855

Abstract: The method for manufacturing the capacitor is provided to form the storage electrode of square pillar shape and to increase the area and to reduce the short failure. The mold layer is formed on the semiconductor substrate(100) including the plug. The mold layer is etched to the first direction. The first mold layer pattern is formed. The first mold layer pattern has the first opening which partly exposes the semiconductor substrate. The first insulating layer filling the first opening is formed. The first and the second insulating layer pattern have the second aperture which partly exposes the semiconductor substrate. The second insulating layer filling the second aperture is formed. The second mold layer pattern is removed by wet type. The third opening whose inner edge part is round and which exposes the plug is formed. The storage electrode(154) is formed on the inner side of the third opening and the exposed plug. The dielectric layer(156) is formed on the storage electrode. The plate electrode is formed on the dielectric layer.

Abstract translation: 设置电容器的制造方法，形成方柱状的储存电极，增加面积，减少短路故障。 模具层形成在包括插头的半导体衬底（100）上。 将模具层蚀刻到第一方向。 形成第一模层图案。 第一模层图案具有部分地暴露半导体衬底的第一开口。 形成填充第一开口的第一绝缘层。 第一和第二绝缘层图案具有部分地暴露半导体衬底的第二孔径。 形成填充第二孔的第二绝缘层。 通过湿式除去第二模层图案。 形成内边缘部分为圆形并暴露于塞子的第三开口。 存储电极（154）形成在第三开口的内侧和暴露的插塞上。 介电层（156）形成在存储电极上。 在电介质层上形成平板电极。

公开(公告)号：KR1020120019877A

公开(公告)日：2012-03-07

申请号：KR1020100083448

申请日：2010-08-27

Applicant: 삼성전자주식회사

Inventor： 임준희 ,  야마다사토루 ,  홍성덕

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10894 ,  H01L21/76264 ,  H01L21/823481 ,  H01L21/76897

Abstract: PURPOSE: A semiconductor device which includes a low resistance region under a device separation film is provided to easily transfer a back bias to an active region by arranging a low resistance region which includes an impurity ion of the same conductivity type as the active region under the device separation film. CONSTITUTION: An adhesive film(27) is arranged on a substrate(31). A wiring layer(25) is arranged on the adhesive film. A buried well(21) which includes first conductivity type impurity ions is arranged on the wiring layer. First and second active regions(15A,15B) which include second conductivity type impurity ions are arranged on the buried well. A device separation film(37) is arranged between the first and second active regions. A low resistance region(39) is arranged between the device separation film and the wiring layer.

Abstract translation: 目的：提供一种在器件分离膜下方包括低电阻区域的半导体器件，以通过布置低电阻区域来容易地将反偏压传递到有源区域，该低电阻区域包括与下面所示的有源区域相同的导电类型的杂质离子 器件分离膜。 构成：粘合膜（27）布置在基底（31）上。 布线层（25）布置在粘合膜上。 包括第一导电型杂质离子的掩埋阱（21）布置在布线层上。 包括第二导电类型的杂质离子的第一和第二有源区（15A，15B）被布置在掩埋阱上。 器件分离膜（37）布置在第一和第二有源区之间。 在器件分离膜和布线层之间布置有低电阻区域（39）。

公开(公告)号：KR101734936B1

公开(公告)日：2017-05-15

申请号：KR1020100083448

申请日：2010-08-27

Applicant: 삼성전자주식회사

Inventor： 임준희 ,  야마다사토루 ,  홍성덕

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10894 ,  H01L21/76264 ,  H01L21/823481

Abstract: 기판상에형성된접착막이제공된다. 상기접착막 상에배선층이배치된다. 상기배선층 상에제1 도전형 불순물이온들을갖는매립웰(buried well)이제공된다. 상기매립웰 상에상기제1 도전형과다른제2 도전형 불순물이온들을갖는제1 및제2 활성영역들이배치된다. 상기제1 및제2 활성영역들사이에소자분리막이배치된다. 상기소자분리막 및상기배선층 사이에저 저항영역이배치된다. 상기저 저항영역에전기적으로접속된백 바이어스배선이제공된다. 상기저 저항영역은상기활성영역들보다높은농도의상기제2 도전형 불순물이온들을갖는다.

Abstract translation: 提供形成在基板上的粘合剂膜。 布线层设置在粘合剂膜上。 现在提供在布线层上具有第一导电类型杂质离子的掩埋阱。 具有不同于第一导电类型的第二导电类型杂质离子的第一和第二有源区被设置在掩埋阱上。 元件隔离膜设置在第一和第二有源区之间。 并且在器件隔离膜和布线层之间设置低电阻区域。 并且提供电连接到低电阻区域的背偏置布线。 并且低电阻区具有比有源区更高浓度的第二导电类型杂质离子。