公开(公告)号：KR1020060130443A

公开(公告)日：2006-12-19

申请号：KR1020050051123

申请日：2005-06-14

Applicant: 삼성전자주식회사

Inventor： 황수만

IPC: G11C11/406

Abstract: A semiconductor memory device having respective self refresh pulses for banks is provided to prevent an excessive current from being applied on the bank by adjusting the period of the self refresh pulse according to the refresh characteristic of the bank. A semiconductor memory device having respective self refresh pulses for banks includes plural self refresh pulse generators(31~34). The self refresh pulse generator generates self refresh pulses having different pulse periods according to the refresh period of the respective banks. The semiconductor memory device includes plural row address counters(41~44), which receive the self refresh pulses, count the received signals, and output row address signals to the respective banks. Plural row decoders(51~54) receive the row address signals and allocate respective rows for the row address signals.

Abstract translation: 提供具有用于存储体的各自的自刷新脉冲的半导体存储器件，以通过根据存储体的刷新特性调整自刷新脉冲的周期来防止过载电流施加到存储体上。 具有各自的自刷新脉冲的半导体存储器件包括多个自刷新脉冲发生器（31〜34）。 自刷新脉冲发生器根据各个存储体的刷新周期产生具有不同脉冲周期的自刷新脉冲。 半导体存储器件包括多个行地址计数器（41〜44），其接收自刷新脉冲，对接收到的信号进行计数，并将行地址信号输出到相应的存储体。 多行解码器（51〜54）接收行地址信号，并为行地址信号分配各行。

公开(公告)号：KR100847315B1

公开(公告)日：2008-07-21

申请号：KR1020070019964

申请日：2007-02-28

Applicant: 삼성전자주식회사

Inventor： 황수만 ,  이호철

IPC: G11C11/401 ,  G11C11/402 ,  G11C11/4074

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4068 ,  G11C11/4085

Abstract: A self refresh control circuit, a semiconductor memory device including the same and a method of controlling self refresh are provided to reduce power consumption and to prevent refresh operation error, by controlling a word line enable signal and voltage supply timing in a self refresh mode. A refresh cycle control part(100a) generates a control signal indicating refresh cycle in response to a self refresh signal. A voltage generator(200a) generates an output voltage boosted at every refresh cycle in response to the control signal. A word line enable circuit(300a) generates a word line enable signal enabled at every refresh cycle after delay time required in boosting an output voltage of the voltage generator in response to the control signal.

Abstract translation: 提供自刷新控制电路，包括该自刷新控制电路的半导体存储器件和控制自刷新的方法，以通过在自刷新模式下控制字线使能信号和电压供给定时来降低功耗并防止刷新操作错误。 刷新周期控制部分（100a）响应于自刷新信号产生指示刷新周期的控制信号。 电压发生器（200a）响应于控制信号产生在每个刷新周期升压的输出电压。 字线使能电路（300a）响应于控制信号，在升压电压发生器的输出电压所需的延迟时间之后，在每个刷新周期产生使能的字线使能信号。

公开(公告)号：KR1020070057336A

公开(公告)日：2007-06-07

申请号：KR1020050116643

申请日：2005-12-01

Applicant: 삼성전자주식회사

Inventor： 황수만 ,  김형동 ,  장영민 ,  김중식

IPC: G11C29/18

Abstract: A memory device having a common fuse block is provided to reduce the size of a memory chip by selectively adopting the function of a row fuse block or a column fuse block through the common fuse block. A bank(410,420,430,440) has a plurality of memory cells arranged in rows and columns. A common fuse block(416) includes a number of fuses, and is arranged in a busing path where row and column address signals of a bank cross each other. A redundancy memory block is arranged adjacent to the common fuse block, and has spare memory cells replacing a defective cell in the bank. The common fuse block includes a multiplexer generating a common fuse signal in response to the row address signals, the column address signals, a row control signal and a column control signal; and a common fuse part generating a row redundancy signal and a column redundancy signal by selectively cutting the fuses in response to the common fuse signal.

Abstract translation: 提供具有公共熔丝块的存储器件，通过选择性地采用行熔丝块或列熔丝块通过公共熔断器块的功能来减小存储器芯片的尺寸。 银行（410,420,430,440）具有以行和列排列的多个存储单元。 共同的保险丝盒（416）包括多个保险丝，并且布置在其中行和列地址信号彼此交叉的通路中。 冗余存储器块被布置为与公共熔丝块相邻，并且具有替换存储体中的有缺陷单元的备用存储器单元。 公共熔丝块包括响应于行地址信号，列地址信号，行控制信号和列控制信号而产生公共熔丝信号的多路复用器; 以及公共熔丝部分，其通过响应于公共熔丝信号选择性地切断熔丝而产生行冗余信号和列冗余信号。

公开(公告)号：KR1020110004084A

公开(公告)日：2011-01-13

申请号：KR1020090061721

申请日：2009-07-07

Applicant: 삼성전자주식회사

Inventor： 황수만

IPC: G11C7/06

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/18

Abstract: PURPOSE: A semiconductor device is provided to reduce current consumption by selectively operating a local sense amplifier which is used. CONSTITUTION: A plurality of control signal generating parts generate an enabled control signal when a column enable signal and a low enable signal are enabled. A plurality of local sense amplifiers(LSA_1) amplify the data of a local input/output line pair and output the data to a global input/output line in response to a control signal corresponding to a read/write signal.

Abstract translation: 目的：提供半导体器件以通过选择性地操作所使用的局部读出放大器来减少电流消耗。 构成：当列使能信号和低使能信号被使能时，多个控制信号产生部分产生使能的控制信号。 多个本地读出放大器（LSA_1）响应于与读/写信号相对应的控制信号，放大本地输入/输出线对的数据并将数据输出到全局输入/输出线。

公开(公告)号：KR100752656B1

公开(公告)日：2007-08-29

申请号：KR1020060017883

申请日：2006-02-23

Applicant: 삼성전자주식회사

Inventor： 김중식 ,  황수만 ,  장영민

IPC: G11C5/14 ,  G11C11/4074

CPC classification number: G11C5/145 ,  G11C11/4074

Abstract: 본 발명은 전하 전달 소자의 바디 바이어스 전압을 선택적으로 제어하는 전하 전달 스위치 회로 및 이를 포함하는 승압 전압 발생 회로에 대하여 개시된다. 전하 전달 스위치 회로는, 전하 전달을 지시하는 제1 제어 신호와 제2 제어 신호에 의해 부스트되는 커패시터와, 전원 전압과 커패시터 사이에 연결되고 프리차아지 신호가 그 게이트에 연결되는 제1 트랜지스터와, 제1 노드와 제2 노드 사이에 연결되고 커패시터의 다른 일단이 그 게이트에 연결되는 제2 트랜지스터와, 제1 노드와 제2 트랜지스터의 벌크 사이에 연결되고 제1 제어 신호가 그 게이트에 연결되는 제3 트랜지스터와, 그리고 제2 트랜지스터의 벌크와 접지 전압 사이에 연결되고 제2 제어 신호가 그 게이트에 연결되는 제4 트랜지스터를 포함한다. 전하 전달 스위치 회로는, 전하 전달시, 제2 트랜지스터의 벌크를 그 드레인인 제1 노드에 연결하여 제2 트랜지스터의 문턱 전압을 낮추어 전하 전달 효율을 높인다. 그리고, 전하 전달 스위치 회로는, 프리차아지 동작시, 제2 트랜지스터의 벌크를 접지 전압으로 연결시켜 제2 트랜지스터의 문턱 전압을 높여 제2 트랜지스터를 통한 전하 역류를 방지한다.
승압 전압 발생 회로, 전하 전달 스위치 회로, 바디 바이어스 전압

公开(公告)号：KR1020070063778A

公开(公告)日：2007-06-20

申请号：KR1020050123986

申请日：2005-12-15

Applicant: 삼성전자주식회사

Inventor： 황형렬 ,  황수만 ,  장영민 ,  김중식

IPC: H03K19/00 ,  H03K17/10

CPC classification number: G11C5/144 ,  G11C5/147 ,  H03K17/063

Abstract: A voltage converter using both standby voltage converter and active voltage converter during power-up is provided to prevent delay due to a difference of an external voltage apply speed and an operation voltage setting speed by simultaneously outputting a standby voltage and an active voltage in a power-up mode. A voltage converter(100) using both standby voltage converter and active voltage converter during power-up includes a standby voltage converter(120) and an active voltage converter(140). The standby voltage converter(120) converts an external voltage to a standby voltage(VSTN) of an operation voltage(VOPE) in a standby mode. The active voltage converter(140) converts the external voltage to an active voltage(VACT) of the operation voltage(VOPE) in an active mode. The voltage converter(100) simultaneously outputs the standby voltage(VSTN) and the active voltage(VACT) in a power-up mode.

Abstract translation: 提供在上电期间使用备用电压转换器和有源电压转换器的电压转换器，以通过同时输出备用电压和有功电压的电力来防止由外部电压施加速度和操作电压设定速度的差异引起的延迟 -up模式。 在上电期间使用备用电压转换器和有源电压转换器的电压转换器（100）包括备用电压转换器（120）和有源电压转换器（140）。 备用电压转换器（120）在待机模式下将外部电压转换为工作电压（VOPE）的待机电压（VSTN）。 有源电压转换器（140）将外部电压转换为工作电压（VOPE）的有效电压（VACT）。 电压转换器（100）在上电模式下同时输出待机电压（VSTN）和有效电压（VACT）。

公开(公告)号：KR1020060088968A

公开(公告)日：2006-08-07

申请号：KR1020050009500

申请日：2005-02-02

Applicant: 삼성전자주식회사

Inventor： 황수만 ,  김형동

IPC: G11C11/401

Abstract: 셀프 리프레시 펄스 생성 장치 및 이를 구비하는 반도체 메모리 장치가 개시되어 있다. 셀프 리프레시 펄스 생성 장치는, 반도체 메모리 장치에 구비된 N개의 뱅크의 셀프 리프레시를 수행하기 위한 표준 셀프 리프레시 펄스를 생성하는 표준 셀프 리프레시 펄스 발생부; 및 상기 생성된 표준 셀프 리프레시 펄스를 입력받고, 상기 각 뱅크의 셀프 리프레시 주기에 따라 상기 입력된 표준 셀프 리프레시 펄스의 주기를 변환시켜 N개의 뱅크 셀프 리프레시 펄스를 생성한 뒤, 상기 생성된 각 뱅크 셀프 리프레시 펄스를 대응되는 뱅크 측으로 전송하는 뱅크별 셀프 리프레시 신호 발생부로 구성된다. 따라서, 각 뱅크의 셀프 리프레시 주기 특성에 따른 각각의 뱅크에 대응되는 뱅크 셀프 리프레시 펄스를 생성하고, 그 주기에 따른 셀프 리프레시를 수행할 수 있다.

公开(公告)号：KR1020080018561A

公开(公告)日：2008-02-28

申请号：KR1020060080855

申请日：2006-08-25

Applicant: 삼성전자주식회사

Inventor： 황수만

IPC: G11C5/14 ,  G11C29/00 ,  G11C7/10

Abstract: A semiconductor device capable of controlling the number of enabled drivers and a method thereof are provided to control the number of drivers enabled according to the variation of operation frequency or surrounding temperature of the semiconductor device. A detection signal generator(11) generates a detection signal by detecting operation frequency of a semiconductor device. A plurality of drivers(15) supplies a corresponding internal voltage to a memory cell array in response to an enable signal. At least one transmission control circuit(13) controls to transmit the enable signal to at least one driver of the plurality of drivers in response to the detection signal.

Abstract translation: 提供能够控制使能驱动器的数量的半导体器件及其方法，以根据半导体器件的工作频率或周围温度的变化来控制使能的驱动器的数量。 检测信号发生器（11）通过检测半导体器件的工作频率来产生检测信号。 响应于使能信号，多个驱动器（15）将相应的内部电压提供给存储单元阵列。 至少一个传输控制电路（13）响应于检测信号控制向多个驱动器中的至少一个驱动器发送使能信号。

公开(公告)号：KR1020070087457A

公开(公告)日：2007-08-28

申请号：KR1020060017883

申请日：2006-02-23

Applicant: 삼성전자주식회사

Inventor： 김중식 ,  황수만 ,  장영민

IPC: G11C5/14 ,  G11C11/4074

CPC classification number: G11C5/145 ,  G11C11/4074 ,  G11C5/147 ,  G11C11/4072

Abstract: A charge transfer switching circuit which controls a body bias voltage of a charge transfer device selectively and a boosting voltage generating circuit including the same are provided to increase charge transfer efficiency during a charge transfer operation by controlling a bulk voltage of a transistor in the charge transfer switching circuit selectively. A first inverter(511) receives a first control signal indicating charge transfer and generates a second control signal. A second inverter(512) receives the second control signal. One end of a capacitor(513) is connected to the output of the second inverter. A first transistor(515) is connected between a power supply voltage and the other end of the capacitor, and a precharge signal is connected to a gate of the first transistor. A second transistor(516) is connected between a first node and a second node, and the other end of the capacitor is connected to a gate of the second transistor. A third transistor(517) is connected between the first node and a bulk of the second transistor, and the first control signal is connected to a gate of the third transistor. A fourth transistor(518) is connected between a bulk of the second transistor and a ground voltage, and the second control signal is connected to a gate of the fourth transistor.

Abstract translation: 选择性地控制电荷转移装置的体偏置电压和包括该电荷转移装置的升压电压产生电路的电荷转移开关电路被提供以通过控制电荷转移中的晶体管的体电压来增加电荷转移操作期间的电荷转移效率 开关电路选择。 第一反相器（511）接收指示电荷转移的第一控制信号并产生第二控制信号。 第二逆变器（512）接收第二控制信号。 电容器（513）的一端连接到第二反相器的输出端。 第一晶体管（515）连接在电源电压和电容器的另一端之间，并且预充电信号连接到第一晶体管的栅极。 第二晶体管（516）连接在第一节点和第二节点之间，电容器的另一端连接到第二晶体管的栅极。 第三晶体管（517）连接在第一节点和第二晶体管的体之间，第一控制信号连接到第三晶体管的栅极。 第四晶体管（518）连接在第二晶体管的大部分和接地电压之间，第二控制信号连接到第四晶体管的栅极。