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    그래핀을 포함하는 반도체 소자 및 그 제조 방법
    2.
    发明公开
    그래핀을 포함하는 반도체 소자 및 그 제조 방법 有权
    包含石墨的半导体器件及其制造方法

    公开(公告)号：KR1020120048241A

    公开(公告)日：2012-05-15

    申请号：KR1020100109778

    申请日：2010-11-05

    Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

    Inventor： 정현종 ,  이재호 ,  이재홍 ,  신형철 ,  서순애 ,  이성훈 ,  허진성 ,  양희준

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/1606 ,  H01L29/41758 ,  H01L29/66477 ,  H01L29/778 ,  H01L29/66431

    Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve applicability of a high speed operation element by forming an inter layer dielectric and a gate insulating layer by using different material. CONSTITUTION: A gate electrode(12) is formed on a substrate(10). The gate electrode comprises a projected gate finger. A gate insulating layer(13) is formed on the gate electrode. An inter-layer insulating film(11) is formed on the side of the gate insulating layer and the gate electrode. The inter-layer insulating film comprises a material having dielectric permittivity lower than the gate insulating layer. A graphene layer(14) is formed on the gate insulating layer and the inter-layer insulating film. A source(15a) and a drain(15b) are formed on the graphene layer. Graphene is formed in the lower side of the graphene layer between the source and drain.

    Abstract translation: 目的：提供半导体器件及其制造方法，以通过使用不同的材料形成层间电介质和栅绝缘层来提高高速工作元件的适用性。 构成：在基板（10）上形成栅电极（12）。 栅极电极包括投影的栅极指状物。 栅极绝缘层（13）形成在栅电极上。 在栅极绝缘层和栅电极的一侧形成层间绝缘膜（11）。 层间绝缘膜包括具有低于栅极绝缘层的介电常数的材料。 在栅极绝缘层和层间绝缘膜上形成石墨烯层（14）。 源极（15a）和漏极（15b）形成在石墨烯层上。 在源极和漏极之间的石墨烯层的下侧形成石墨烯。

    튜너블 배리어를 구비한 그래핀 스위칭 소자
    4.
    发明公开
    튜너블 배리어를 구비한 그래핀 스위칭 소자 审中-实审
    具有可调节障碍物的石墨切换装置

    公开(公告)号：KR1020140054744A

    公开(公告)日：2014-05-09

    申请号：KR1020120120611

    申请日：2012-10-29

    Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

    Inventor： 이재호 ,  박성준 ,  변경은 ,  서형석 ,  송현재 ,  신형철 ,  이재홍 ,  정현종 ,  허진성

    IPC: H01L29/08 ,  H01L29/12

    CPC classification number: H01L29/78 ,  H01L29/1606 ,  H01L29/407 ,  H01L29/66977 ,  H01L29/772 ,  H01L29/872 ,  H01L29/88

    Abstract: Disclosed is a graphene switching device having a tunable barrier. The disclosed graphene switching device includes a first electrode and an insulating layer which are respectively arranged in a first region and a second region which are separated from each other on a conductive semiconductor substrate, a graphene layer which is extended from the insulating layer to the first electrode on the substrate and is separated from the first electrode, a second electrode which faces the insulating layer on the graphene layer, a gate electrode above the graphene layer, and a first well which has a region of the substrate which touches the lower part of the graphene layer which is doped with impurity. The first wall has an energy barrier which is between the graphene layer and the first electrode.

    Abstract translation: 公开了一种具有可调屏障的石墨烯开关装置。 所公开的石墨烯开关装置包括分别布置在导电半导体衬底上彼此分离的第一区域和第二区域中的第一电极和绝缘层，从绝缘层延伸到第一区域的石墨烯层 电极与第一电极分离，面对石墨烯层上的绝缘层的第二电极，石墨烯层上方的栅极电极和第一阱，该第一阱具有接触下述部分的基板的下部 掺杂有杂质的石墨烯层。 第一壁具有在石墨烯层和第一电极之间的能量势垒。

    복수의 그래핀 채널층을 구비하는 그래핀 전자소자
    8.
    发明公开
    복수의 그래핀 채널층을 구비하는 그래핀 전자소자 有权
    包含多个石墨通道层的石墨电子器件

    公开(公告)号：KR1020120076061A

    公开(公告)日：2012-07-09

    申请号：KR1020100138041

    申请日：2010-12-29

    Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

    Inventor： 정현종 ,  이재홍 ,  이재호 ,  신형철 ,  서순애 ,  이성훈 ,  허진성 ,  양희준

    IPC: H01L29/78

    CPC classification number: H01L29/1606 ,  H01L29/41733 ,  H01L29/66045 ,  H01L29/778 ,  H01L29/78684 ,  H01L29/78696 ,  H01L21/823412

    Abstract: PURPOSE: A graphene electric component equipped with a plurality of graphene channel layers is provided to increase current transition speed between a drain electrode and a source electrode by forming the plurality of graphene channel layers into a double layer structure. CONSTITUTION: A gate electrode(120) is formed on a substrate(110). A first gate insulating layer(131) covering the gate electrode is formed on the substrate. A first graphene channel layer(141) is formed on the first gate insulating layer. A second gate insulating layer(132) is formed on the first graphene channel layer. A second graphene channel layer(142) is formed on the second gate insulating layer. A source electrode(150) and a drain electrode(160) are formed on the first graphene channel layer and the second graphene channel layer.

    Abstract translation: 目的：提供装配有多个石墨烯通道层的石墨烯电气部件，以通过将多个石墨烯通道层形成双层结构来增加漏电极和源电极之间的电流转变速度。 构成：在基板（110）上形成栅电极（120）。 在基板上形成覆盖栅电极的第一栅极绝缘层（131）。 在第一栅绝缘层上形成第一石墨烯通道层（141）。 第一栅极绝缘层（132）形成在第一石墨烯沟道层上。 在第二栅绝缘层上形成第二石墨烯通道层（142）。 源电极（150）和漏电极（160）形成在第一石墨烯沟道层和第二石墨烯沟道层上。

    분리 절연막 스택으로 둘러싸인 차폐전극을 갖는 3차원 수직형 메모리 셀 스트링, 이를 이용한 메모리 어레이 및 그 제조 방법
    9.
    发明授权
    분리 절연막 스택으로 둘러싸인 차폐전극을 갖는 3차원 수직형 메모리 셀 스트링, 이를 이용한 메모리 어레이 및 그 제조 방법 有权
    具有屏蔽电极的三维垂直型存储单元，通过隔离介质堆叠，使用其的存储器阵列及其制造方法

    公开(公告)号：KR101056113B1

    公开(公告)日：2011-08-10

    申请号：KR1020100063958

    申请日：2010-07-02

    Applicant: 서울대학교산학협력단

    Inventor： 이종호 ,  신형철

    IPC: H01L27/115 ,  H01L21/8247 ,  H01L27/10

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11578

    Abstract: PURPOSE: A 3D vertical type memory cell string with shield electrode surrounded by a isolation insulating layer stack, a memory array using the same and a manufacturing method thereof are provided to solve the threshold voltage dissemination problem of stacks by injecting charges into the charge storage node in the isolation insulating layer stack as well as completely eliminate electrical interference which occurs in semiconductor bodies in both sides of each trench. CONSTITUTION: Two or more electrode stacks are separated by one or more trenches at a certain distance on a semiconductor substrate(1) and are formed by repeatedly laminating an insulating layer and a conductive material layer(10) to the vertical direction by turns. A gate insulating layer stack includes a charge storage layer which is formed on the top and the side of each electrode stack and the separated space of the substrate. A semiconductor body(5) is formed on the gate insulating layer stack. A shield electrode(27) is formed by placing the isolation insulating layer for each trench on the semiconductor body. The isolation insulating layer includes the charge storage node.

    Abstract translation: 目的：提供一种具有由隔离绝缘层堆叠围绕的屏蔽电极的3D垂直型存储单元串，使用其的存储器阵列及其制造方法，以通过向电荷存储节点注入电荷来解决堆叠的阈值电压传播问题 在隔离绝缘层堆叠中，并且完全消除了在每个沟槽两侧的半导体本体中发生的电气干扰。 构成：在半导体衬底（1）上将两个或多个电极堆叠在一定距离上由一个或多个沟槽隔开，并且通过反复层叠垂直方向的绝缘层和导电材料层（10）而形成。 栅极绝缘层堆叠包括形成在每个电极堆叠的顶部和侧面以及衬底的分离空间的电荷存储层。 在栅极绝缘层堆叠上形成半导体本体（5）。 通过将用于每个沟槽的隔离绝缘层放置在半导体本体上来形成屏蔽电极（27）。 隔离绝缘层包括电荷存储节点。

    메모리 셀 스트링 스택 및 이를 이용한 메모리 어레이
    10.
    发明授权
    메모리 셀 스트링 스택 및 이를 이용한 메모리 어레이 有权
    MEMORY CELL STRING STACK和MEMORY ARRAY WITH THE SAME

    公开(公告)号：KR101091023B1

    公开(公告)日：2011-12-09

    申请号：KR1020100099171

    申请日：2010-10-12

    Applicant: 서울대학교산학협력단

    Inventor： 이종호 ,  이주완 ,  신형철

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/2463 ,  H01L21/28273 ,  H01L21/823475 ,  H01L27/2436

    Abstract: PURPOSE: A memory cell string stack and a memory array using the same are provided to cut off charge transfer between a top cell unit and a bottom cell unit by not connecting charge storage nodes between cell units which are formed in the top part and the bottom part. CONSTITUTION: A semiconductor stack(40) is formed by alternatively laminating an insulating layer(2) and a semiconductor layer(3) on a semiconductor substrate(1). A gate insulating layer stack(7) includes a plurality of charge storage layers(5). An isolation insulating layer(9) is filled between the control electrodes and between the gate insulating layer stacks. A storing layer for each charge of the gate insulating layer stack is formed in a recess.

    Abstract translation: 目的：提供存储单元串栈和使用其的存储器阵列，以通过不在顶部和底部形成的单元单元之间连接电荷存储节点来切断顶单元单元和底单元单元之间的电荷转移 部分。 构成：通过在半导体衬底（1）上交替地层叠绝缘层（2）和半导体层（3）来形成半导体堆叠（40）。 栅极绝缘层堆叠（7）包括多个电荷存储层（5）。 隔离绝缘层（9）填充在控制电极之间和栅极绝缘层堆叠之间。 在凹部中形成用于栅极绝缘层堆叠的每个电荷的存储层。

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