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公开(公告)号：KR1020090084382A
公开(公告)日：2009-08-05
申请号：KR1020080010538
申请日：2008-02-01
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
CPC classification number: H04L27/2688 , H04L27/2659 , H04L27/2672 , H04L27/2675
Abstract: A correlation apparatus for frequency synchronization in a broadband wireless access communication system and a correlation method thereof are provided to improve the frequency synchronization performance by performing the frequency synchronization according to the highest correlation value. A frequency synchronizing unit(300) includes a delay and conjugate complex processor(350) and a correlator(340). The delay and conjugate complex processor delays as much as the predetermined interval after the FFT(Fast Fourier Transform) and generates a first signal by multiplying the signal after the FFT(Fast Fourier Transform) processing by the conjugate complex processed reception signal. The correlation unit receives a first signal, a second signal, and a third signal, and obtains the highest correlation value by producing the differential correlation value about the first signal and third signal. The second signal is generated by multiplying the conjugate complex of the reference signal by the delayed signal based on the reference signal. The third signal is produced by the signal delaying the second signal by the conjugate complex signal. A frequency controller(330) performs the frequency synchronization according to the highest correlation value.
Abstract translation: 提供宽带无线接入通信系统中的频率同步的相关装置及其相关方法，以通过根据最高相关值执行频率同步来提高频率同步性能。 频率同步单元（300）包括延迟和共轭复合处理器（350）和相关器（340）。 延迟和共轭复合处理器在FFT（快速傅立叶变换）之后的预定时间间隔延迟并且通过将FFT（快速傅里叶变换）处理之后的信号乘以共轭复数处理的接收信号而产生第一信号。 相关单元接收第一信号，第二信号和第三信号，并且通过产生关于第一信号和第三信号的差分相关值来获得最高相关值。 通过基于参考信号将参考信号的共轭复乘乘以延迟的信号来产生第二信号。 第三信号由通过共轭复信号延迟第二信号的信号产生。 频率控制器（330）根据最高的相关值进行频率同步。
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公开(公告)号：KR101421406B1
公开(公告)日：2014-07-23
申请号：KR1020080010538
申请日：2008-02-01
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
CPC classification number: H04L27/2688 , H04L27/2659 , H04L27/2672 , H04L27/2675
Abstract: 본 발명은 주파수 동기를 위한 상관 방법에 관한 것으로, 광대역 무선접속 통신시스템에서 수신기의 주파수 동기 방법에 있어서 수신한 신호와 기준신호 사이에 가변 간격의 차동 상관을 수행하여 가장 상관도가 높은 값을 구하는 과정과 상기 가장 상관도가 높은 값에 따라 주파수 동기를 수행하는 과정을 포함하는 것으로 다중 경로 페이딩이 존재하는 직교 주파수 분할 다중 전송 시스템의 실제 수신환경에서 대략적 주파수 동기 성능을 크게 향상시킬 수 있는 이점이 있다.
OFDM, 주파수 동기, CAZAC, FFT-
公开(公告)号：KR1020090065661A
公开(公告)日：2009-06-23
申请号：KR1020070133073
申请日：2007-12-18
Applicant: 삼성전자주식회사
CPC classification number: H04L27/2614 , H03M1/662 , H03M1/70 , H04L5/0044 , H04L27/2626
Abstract: A method and an apparatus for reducing the number of bits for digital to analog conversion in a frequency division multiple access system are provided to control a power level of a signal inputted to a digital to analog converter into a fixed level by controlling a gain of signals. A dynamic range preprocessing part(401) controls and processes a gain of signals in order to always maintain a power of signals into a fixed level regardless of kind and quota of signals. A digital gain standardization part(403) controls the gain of the signals by using a DG(Digital Gain) value of the dynamic range preprocessing part. The digital gain standardization part controls a power level of the signals into a level of a minimum allocation regardless of quota. A digital to analog converting part(405) converts a standardized digital signal into an analog signal. An analog gain correcting part(407) controls the gain of the analog signal of the digital to analog converting part according to an AG(Analog Gain) value of the dynamic range preprocessing part.
Abstract translation: 提供一种用于减少频分多址系统中的数模转换的位数的方法和装置，以通过控制信号增益来控制输入到数模转换器的信号的功率电平为固定电平 。 动态范围预处理部分（401）控制和处理信号的增益，以便始终将信号的功率保持在固定的水平，而不管信号的种类和配额。 数字增益标准化部件（403）通过使用动态范围预处理部件的DG（数字增益）值来控制信号的增益。 数字增益标准化部分将信号的功率电平控制为最小分配的水平，而不管配额如何。 数模转换部（405）将标准数字信号转换为模拟信号。 模拟增益校正部件（407）根据动态范围预处理部件的AG（模拟增益）值来控制数模转换部件的模拟信号的增益。
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公开(公告)号：KR1020030031425A
公开(公告)日：2003-04-21
申请号：KR1020020062303
申请日：2002-10-12
Applicant: 삼성전자주식회사
IPC: H04B1/40
CPC classification number: H01Q1/362 , H01Q1/243 , H01Q1/244 , H01Q11/08 , H04B1/3805 , H04M2250/10
Abstract: PURPOSE: A mobile communication device having a multi-band antenna is provided to adopt an integrated antenna capable of receiving CDMA(Code Division Multiple Access), PCS(Personal Communication Service) and GPS(Global Positioning System) bands of signals in a dual helical structure. CONSTITUTION: A GPS processor(100) inputs the first frequency band of signals to generate terrestrial determination information. A call signal processing part inputs and demodulates the second frequency band of signals and the third frequency band of signals or modulates signals to be transmitted, to output the second or third frequency band of signals, wherein the second frequency band is lower than the first frequency band and the third frequency band is higher than the first frequency band. A multi-band antenna(12) has dual pitch helical in which two helical coils having mutually different impedance for the first and third frequency bands and the second frequency band are serially connected, and transceives multi-frequency bands of signals including the first to third frequency bands. A frequency band dividing part separates the first frequency band of signals from the signals received from the multi-band antenna(12) for supply to the GPS processor(100), divides the second frequency band of signals and the third frequency band of signals for supply to the call signal processing part, and supplies signals outputted from the call signal processing part to the multi-band antenna(12). And a controller(90) controls the GPS processor(100) and the call signal processing part.
Abstract translation: 目的：提供一种具有多频带天线的移动通信设备，以采用能够以双螺旋线接收CDMA（码分多址），PCS（个人通信服务）和GPS（全球定位系统）信号频带的集成天线 结构体。 构成：GPS处理器（100）输入信号的第一频带以产生地面确定信息。 呼叫信号处理部分输入和解调信号的第二频带和信号的第三频带或调制要发送的信号，以输出信号的第二或第三频带，其中第二频带低于第一频率 并且第三频带高于第一频带。 多频带天线（12）具有双音调螺旋，其中对于第一和第三频带和第二频带的两个具有相互不同阻抗的螺旋线圈串联连接，并且收发包括第一至第三的信号的多频带 频带。 频带分割部将从用于提供的多频带天线（12）的信号的信号的第一频带分离为GPS处理器（100），将信号的第二频带和第三频带信号分割为 提供给呼叫信号处理部分，并将从呼叫信号处理部分输出的信号提供给多频带天线（12）。 并且控制器（90）控制GPS处理器（100）和呼叫信号处理部分。
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公开(公告)号：KR1020090008692A
公开(公告)日：2009-01-22
申请号：KR1020070071844
申请日：2007-07-18
Applicant: 삼성전자주식회사
CPC classification number: G06F17/141
Abstract: A butterfly operating apparatus for pipelined discrete Fourier transformation and a method thereof are provided to reduce the number of multipliers relatively more complicated than an adder, thereby performing an operation with small power. A first adding unit the first input complex number, the second input complex number and the third input complex number. A first multiplying unit multiplies real number and imaginary numbers of the second input complex number with real number and imaginary numbers of a first twiddle factor to output the multiplication of the first twiddle factor and the second input complex number as a first result complex number. And the first multiplying unit outputs the multiplication of a conjugate complex number of the first twiddle factor with the second input complex number as a second result complex number. The second multiplying unit multiplies real number and imaginary numbers of the third input complex number with real number and imaginary numbers of the second twiddle factor to output the multiplication of the second twiddle factor and the third input complex number as a third result complex number. And the second multiplying unit outputs the multiplication of a conjugate complex number of the second twiddle factor with the third input complex number as a fourth result complex number.
Abstract translation: 提供了一种用于流水线离散傅立叶变换的蝶形运算装置及其方法，以减少比加法器复杂得多的乘法器的数量，从而以小功率进行运算。 第一个加法单元，第一个输入复数，第二个输入复数和第三个输入复数。 第一乘法单元将第二输入复数的实数和虚数与第一旋转因子的实数和虚数相乘，以输出第一旋转因子和第二输入复数的乘法作为第一结果复数。 并且第一乘法单元输出第一旋转因子的共轭复数与第二输入复数的乘法作为第二结果复数。 第二乘法单元将第三输入复数的实数和虚数与第二旋转因子的实数和虚数相乘，以输出第二旋转因子和第三输入复数的相乘作为第三结果复数。 并且第二乘法单元输出第二旋转因子的共轭复数与第三输入复数的乘法作为第四结果复数。
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Patent Agency Ranking
公开(公告)号：KR100713506B1
公开(公告)日：2007-04-30
申请号：KR1020050060456
申请日：2005-07-05
Applicant: 삼성전자주식회사
IPC: H04L27/26
CPC classification number: H04L27/2607 , H04L5/023 , H04L27/2634
Abstract: 본 발명은 직교 주파수 분할 다중 접속(OFDMA: Orthogonal Frequency Division Multiple Access) 방식을 사용하는 광대역 무선 접속(BWA: Broadband Wireless Access) 통신 시스템에서 시간 윈도윙(windowing) 처리를 하여 신호를 송신하는 방법 및 장치에 관한 것이다. 이를 위해 본 발명은, 통신 시스템에서 신호를 송신하는 방법에 있어서, 보호 구간 및 상기 보호 구간과 연속되는 유효 심볼 구간을 포함하는 현재 심볼의 이전 심볼에 포함된 제1구간의 신호를 상기 이전 심볼 구간의 신호로 저장하는 과정과, 상기 이전 심볼과 연속되는 상기 현재 심볼에 포함된 제2구간의 신호에 상기 저장된 제1구간의 신호를 중첩하여 상기 현재 심볼의 윈도윙 처리를 하고, 상기 윈도윙 처리된 신호를 송신하는 과정을 포함한다.
광대역 무선 통신 시스템, 직교 주파수 분할 다중(OFDM: Orthogonal Frequency Division Multiplexing), 윈도윙, 에러 벡터 크기(Error Vector Magnitude: EVM).-
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公开(公告)号：KR101359033B1
公开(公告)日：2014-02-11
申请号：KR1020070096284
申请日：2007-09-21
Applicant: 삼성전자주식회사
IPC: G06F17/14
Abstract: 본 발명은 이산 푸리에 변환 장치 및 방법에 관한 것으로, 이산 푸리에 변환 길이를 확인하고 이를 인수분해하여 소수(prime number)의 조합으로 나누는 인수분해부와, 상기 인수분해부에서 나눈 상기 소수의 조합 정보를 이용하여 필요로하는 스테이지 수와 필요로 하는 래딕스(Radix)들을 확인하여 연산할 가변 래딕스 버터플라이를 선택하고 상기 선택한 가변 래딕스 버터플라이의 래딕스를 설정하는 스테이지 제어부와, 상기 스테이지 제어부로부터 연산의 동작여부와 동작할 래딕스 값을 선택받고 선택받은 래딕스로 버터플라이 연산을 수행하는 상기 가변 래딕스 버터플라이를 포함하여서 스테이지를 줄임으로 하드웨어이 낭비를 줄이는 효과가 있다.
이산 푸리에 변환, DFT(Discrete Fourier Transform), 버터플라이-
公开(公告)号：KR1020100129416A
公开(公告)日：2010-12-09
申请号：KR1020090047971
申请日：2009-06-01
Applicant: 삼성전자주식회사
CPC classification number: G06F1/1624 , G06F3/0233
Abstract: PURPOSE: An input mode operating method of a portable terminal including a plurality of input units in order to easily convert an input mode is provided to form an optimum key input environment in the converted input mode. CONSTITUTION: An input screen is displayed as a first input mode(220). A menu screen is displayed by matching one function of a mobile terminal with a key consisting of a first input unit. It determines whether a second input mode is in an active state(230). If so, the displayed input screen is displayed after converting the input screen to a second input screen(240).
Abstract translation: 目的：提供一种包括多个输入单元以便容易地转换输入模式的便携式终端的输入模式操作方法，以在转换的输入模式中形成最佳键输入环境。 构成：输入画面显示为第一输入模式（220）。 通过将移动终端的一个功能与由第一输入单元组成的键进行匹配来显示菜单屏幕。 它确定第二输入模式是否处于活动状态（230）。 如果是，则在将输入画面转换为第二输入画面（240）之后显示所显示的输入画面。
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公开(公告)号：KR1020090030759A
公开(公告)日：2009-03-25
申请号：KR1020070096284
申请日：2007-09-21
Applicant: 삼성전자주식회사
IPC: G06F17/14
CPC classification number: G06F17/141
Abstract: A Discrete Fourier Transform apparatus and a method are provided to minimize a number of butterfly stages by using a variable radix butterfly. A Discrete Fourier Transform apparatus comprises a factorization unit(200), a stage control unit(210), a variable radix butterfly(212~220), and an index sorting unit(250). The factorization unit provides a combination of a prime number to the stage control unit and the index sorting unit, when a size of Discrete Fourier Transform point N is confirmed. The stage control unit selects a variable radix butterfly to be computed by confirming a number of necessary butterfly when receiving combination information of a prime number, and sets up the radix of the selected variable radix butterfly. The variable radix butterfly performs a butterfly operation by using the radix which is set up by the stage control unit. A plurality of butterfly is connected through a pipeline. Each butterfly outputs inputted data after butterfly computation.
Abstract translation: 提供一种离散傅立叶变换装置和方法，通过使用可变的基数蝴蝶来最小化多个蝴蝶阶段。 离散傅立叶变换装置包括分解单元（200），级控制单元（210），可变基数蝶形（212〜220）和索引分类单元（250）。 当确定离散傅里叶变换点N的大小时，分解单元提供素数与舞台控制单元和索引分类单元的组合。 舞台控制单元在接收素数的组合信息时，通过确认必需的蝴蝶数来选择要计算的可变基数蝴蝶，并且设置所选择的变量小数蝴蝶的基数。 可变基数蝶形通过使用由级控制单元设置的基数来执行蝶形运算。 多个蝴蝶通过管道连接。 蝴蝶计算后，每个蝶形输出输入的数据。
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