公开(公告)号：KR101939147B1

公开(公告)日：2019-01-16

申请号：KR1020120024299

申请日：2012-03-09

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 이승훈 ,  송정은

IPC: G05F1/46 ,  G11C5/14 ,  G11C11/4074

公开(公告)号：KR1020130103010A

公开(公告)日：2013-09-23

申请号：KR1020120024299

申请日：2012-03-09

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 이승훈 ,  송정은

IPC: G05F1/10 ,  G05F1/565

CPC classification number: G05F1/465 ,  G11C5/146 ,  G11C11/4074

Abstract: PURPOSE: A variable reference voltage generation circuit and an analog-to-digital converter including the same eliminate the need for a low-voltage transistor because a voltage margin from a ground voltage or a power voltage is always the same with a fixed common mode voltage, thereby reducing manufacturing costs. CONSTITUTION: A variable reference voltage generation circuit includes a level shifter (100) generating a first reference voltage and a second reference voltage converted from a control voltage which is input and a voltage driver (200) generating a third reference voltage and a fourth reference voltage converted from the first reference voltage and the second reference voltage which are input, respectively. The first reference voltage and the second reference voltage are complementary to each other.

Abstract translation: 目的：可变参考电压产生电路和包括该参考电压产生电路的模数转换器消除了对低电压晶体管的需要，因为来自接地电压或电源电压的电压余量与固定共模电压总是相同 ，从而降低制造成本。 构成：可变参考电压产生电路包括产生第一参考电压的电平转换器（100）和从输入的控制电压转换的第二参考电压和产生第三参考电压和第四参考电压的电压驱动器（200） 分别从输入的第一参考电压和第二参考电压转换。 第一参考电压和第二参考电压彼此互补。

公开(公告)号：KR101287097B1

公开(公告)日：2013-07-16

申请号：KR1020120005252

申请日：2012-01-17

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  박혜림 ,  남상필 ,  송정은

IPC: H03M1/38

CPC classification number: H03M1/1205 ,  H03M1/0607 ,  H03M1/38 ,  H03M2201/2233 ,  H03M2201/615

Abstract: PURPOSE: A four channel pipe line SAR ADC minimized mismatching between channels is provided to remove amplifier offset mismatching between channels and to minimize electricity consumption and an area. CONSTITUTION: Four channel pipe line SAR ADC comprises a first SAR ADC (100), a remaining voltage amplifier (110), a second SAR ADC (120) and a digital correction circuit (130). For pieces of 6 bit SAR ADC in the first step is composed of SAR ADC with four channels connected in parallel. The remaining voltage amplifier is connected to an output unit of the first SAR ADC and is shared in four channels with a couple of input units. The second SAR ADC is composed of SAR ADC in four channels connected in parallel which tests remaining voltage which is amplified in the remaining voltage amplifier. The digital correction circuit corrects errors of digital output which comes out of the first SAR ADC and the second SAR ADC.

Abstract translation: 目的：四通道管线SAR ADC最小化通道之间的失配，以消除通道之间的放大器偏移不匹配，并最大限度地减少用电量和面积。 构成：四通道管线SAR ADC包括第一SAR ADC（100），剩余电压放大器（110），第二SAR ADC（120）和数字校正电路（130）。 对于6位SAR ADC，第一步由具有四个通道并联的SAR ADC组成。 剩余的电压放大器连接到第一SAR ADC的输出单元，并在四个通道中共享几个输入单元。 第二个SAR ADC由四路并联的SAR ADC组成，测试剩余电压放大器中剩余的电压。 数字校正电路校正了从第一SAR ADC和第二SAR ADC引出的数字输出的误差。

公开(公告)号：KR101162719B1

公开(公告)日：2012-07-05

申请号：KR1020110049807

申请日：2011-05-25

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 황원석 ,  이승훈 ,  송정은 ,  황동현

IPC: H03M1/12

CPC classification number: H03M1/145 ,  H03F1/0261 ,  H03F3/45 ,  H03F3/45183 ,  H03M1/1225 ,  H03M1/168

Abstract: PURPOSE: An amplifying circuit and an analog digital converting circuit including the same are provided to efficiently reduce a consumable current of an analog to digital converter in a pipeline architecture by sharing the amplifying circuit. CONSTITUTION: A first amplifying circuit(240) comprises first and second rod parts(10,20), an output part(30), first and second input parts(40,50), and a first constant current source part(60). The first load part includes first to third transistors(T1-T3). The second rod parting includes fourth to sixth transistors(T4-T6). An output part includes two seventh to two tenth transistors(T7-T10) which are serially connected, respectively. The first input part includes eleventh to thirteenth transistors(T11-T13). The second input part includes fourteenth to sixteenth transistors(T14-T16). The first constant current part includes seventeenth to nineteenth transistors(T17-T19). A second amplifying circuit(250) includes third and fourth load parts(80,90), an third input part(70), and a second static current source part(95).

Abstract translation: 目的：提供一种放大电路和包括该放大电路的模拟数字转换电路，以通过共享放大电路来有效降低流水线架构中的模数转换器的消耗电流。 构成：第一放大电路（240）包括第一和第二杆部分（10,20），输出部分（30），第一和第二输入部分（40,50）和第一恒定电流源部分（60）。 第一负载部分包括第一至第三晶体管（T1-T3）。 第二棒分离包括第四至第六晶体管（T4-T6）。 输出部分分别包括串联连接的两个第七至第二十个晶体管（T7-T10）。 第一输入部包括第十一至第十三晶体管（T11-T13）。 第二输入部包括第十四至第十六晶体管（T14-T16）。 第一恒定电流部分包括第十七至第十九晶体管（T17-T19）。 第二放大电路（250）包括第三和第四负载部分（80,90），第三输入部分（70）和第二静态电流源部分（95）。