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公开(公告)号：KR1020110090669A
公开(公告)日：2011-08-10
申请号：KR1020100010598
申请日：2010-02-04
Applicant: 건국대학교 산학협력단 , 광운대학교 산학협력단
CPC classification number: H03M1/46 , H03M1/002 , H03M1/361 , H03M2201/2216 , H03M2201/2233 , H03M2201/62
Abstract: PURPOSE: An ADC(Analog to Digital Converter) with a successive approximation register is provided to reduce a design area by simply changing the structure of an analog to digital converter with a SAR(Successive Approximation Register). CONSTITUTION: A reference unit(100) generates the reference voltage of a conversion section. A timing unit(500) generates the reference time for the total conversion process of an analog input signal. A digital error correction unit(600) mixes conversion codes in a digital part based on the reference generated in the timing unit. The digital error correction unit generates the digital total conversion codes of the analog input signal. The conversion codes in a digital part are generated in a first flash ADC(ANALOG TO DIGITAL CONVERTER,200) and a second flash ADC(300).
Abstract translation: 目的：提供具有逐次逼近寄存器的ADC（模数转换器），通过简单地通过SAR（连续逼近寄存器）改变模数转换器的结构来减少设计区域。 构成：参考单元（100）产生转换部分的参考电压。 定时单元（500）产生模拟输入信号的总转换处理的基准时间。 数字纠错单元（600）基于在定时单元中生成的参考来混合数字部分中的转换代码。 数字纠错单元产生模拟输入信号的数字总转换代码。 数字部分中的转换代码在第一闪存ADC（模拟到数字转换器，200）和第二闪存ADC（300）中生成。
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2.发明授权
公开(公告)号：KR100875140B1
公开(公告)日：2008-12-22
申请号：KR1020070110986
申请日：2007-11-01
Applicant: 실리콤텍(주)
IPC: H04N5/335 , G06F3/0354
CPC classification number: H04N5/335 , H01L27/0222 , H03M1/462 , H03M2201/2233
Abstract: A low power image sensor in which a reference voltage is automatically adjusted and an integrated circuit integrating the image sensor on one chip are provided to remove a preprocessor having a large chip size and large power consumption to reduce raw costs of an optical pointing image sensor drastically and minimize power consumption. An image sensor unit(100) senses light from a subject and converts and outputs it into an electric signal. A comparing unit(200) receives an electric signal from the image sensor. The comparing unit compares a voltage level of the electric signal with a reference voltage, and then outputs an image signal at 1 bit/pixel. An effective image adjusting unit(300) compares bit value distribution of the image signal outputted from the comparing unit with an effective range to adjust the reference voltage, thereby outputting an effective image.
Abstract translation: 提供自动调整参考电压的低功率图像传感器，并且将集成图像传感器的集成电路设置在一个芯片上以去除具有大芯片尺寸和大功率消耗的预处理器，以大幅度降低光学指向图像传感器的原始成本 并最大限度地降低功耗。 图像传感器单元（100）感测来自被摄体的光并将其转换并输出为电信号。 比较单元（200）从图像传感器接收电信号。 比较单元将电信号的电压电平与参考电压进行比较，然后以1位/像素输出图像信号。 有效图像调整单元（300）将从比较单元输出的图像信号的比特值分布与有效范围进行比较，以调整参考电压，从而输出有效图像。
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公开(公告)号：KR1020060119242A
公开(公告)日：2006-11-24
申请号：KR1020050041928
申请日：2005-05-19
Inventor： 최중호
IPC: H03M5/12
CPC classification number: H03M5/12 , H03M2201/2233 , H03M2201/4155 , H03M2201/63
Abstract: A frequency tuning circuit of a continuous-time analog filter using an SAR(Successive Approximation Register) scheme is provided to complete frequency tuning efficiently in a short time even at a high tuning resolution by generating a tuning code of an integrator used in the frequency tuning circuit by using the SAR scheme. A frequency tuning circuit of a continuous-time analog filter of an active-RC type generates a frequency tuning code by using an SAR(Successive Approximation Register) scheme. A frequency tuning code generator determines a code of each bit in sequence as decreasing binary weight starting from an uppermost bit. The frequency tuning time takes as long as N clock periods.
Abstract translation: 提供使用SAR（逐次近似寄存器）方案的连续时间模拟滤波器的频率调谐电路，通过生成用于频率调谐的积分器的调谐码，即使在高调谐分辨率下也能在短时间内有效地完成频率调谐 电路采用SAR方案。 有源RC型连续时间模拟滤波器的频率调谐电路通过使用SAR（连续近似寄存器）方案产生频率调谐码。 频率调谐码发生器根据从最高位开始减少的二进制加权，依次确定每个比特的码。 频率调谐时间需要N个时钟周期。
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公开(公告)号：KR1020160093159A
公开(公告)日：2016-08-08
申请号：KR1020150013547
申请日：2015-01-28
Applicant: 삼성디스플레이 주식회사
IPC: H03M1/38
CPC classification number: H03M1/44 , H03M1/462 , H03M1/468 , H03M1/38 , H03M2201/2233
Abstract: 본발명의일 실시예는아날로그입력전압을 N 비트의출력디지털코드로변환하는아날로그-디지털변환기로서, 상기아날로그입력전압및 제1 기준전압을입력받고, 샘플링동작및 홀딩동작을통하여제1 노드의전압의레벨을상기아날로그입력전압의음수의레벨로결정하고, 상기제1 노드의전압의레벨을상기제1 기준전압의레벨을기초로조정해가면서연속근사방법(successive approximation method)을사용하여하나의연속근사사이클마다상기 N 비트의출력디지털코드의하나의비트에대응하는출력논리값을결정하는연속근사변환부, 상기제1 노드의전압의레벨을제2 기준전압의레벨과비교하여비교논리값을생성하는전압비교부, 및상기출력논리값또는상기비교논리값이특정조건을만족하는경우, 상기연속근사방법을통한아날로그-디지털변환과정을종료하고상기 N 비트의출력디지털코드를결정하는제어부를포함하는, 아날로그-디지털변환기를개시한다.
Abstract translation: 本发明的一个实施例涉及将模拟输入电压转换成N位的输出数字码的模数转换器。 公开了一种模数转换器，包括：逐次逼近转换单元，其接收模拟输入电压和第一参考电压，通过一个第一节点将第一节点的电压电平确定为模拟输入电压的负电平 采样操作和保持操作，并且通过使用逐次逼近方法来确定对应于每个逐次逼近周期的N位的输出数字码的一位的输出逻辑值，同时基于第一节点调整第一节点的电压电平 第一参考电压的电平; 电压比较单元，其通过将所述第一节点的电压的电平与第二参考电压的电平进行比较来生成比较逻辑值; 以及控制单元，当输出逻辑值或比较逻辑值满足特定条件时，使用逐次逼近方法终止模数转换处理，并确定N位的输出数字码。
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公开(公告)号：KR1020120073836A
公开(公告)日：2012-07-05
申请号：KR1020100135721
申请日：2010-12-27
Applicant: 주식회사 실리콘웍스
IPC: H03M1/38
CPC classification number: H03M1/38 , H03M1/14 , H03M1/187 , H03M2201/2233 , H03M2201/62 , H03M2201/93
Abstract: PURPOSE: A SAR(Successive Approximation Register) ADC(Analog To Digital Converter) is provided to reduce an installation space by using voltage division resistance instead of using a capacitor array. CONSTITUTION: A preamp part(210) includes first and second MOS transistors(M1,M2) differentially amplify a positive input voltage and a negative input voltage, respectively. A digital/analog converter(240) includes third and fourth MOS transistors(M3,M4) which differentially amplify the output voltage of a voltage divider(241). A SAR control unit(230) outputs a distribution voltage selection signal for selecting a positive DA voltage and a negative DA voltage according to output bit values of a quantizer(220). The quantizer outputs bit values by comparing output currents. The D/A converter selects the positive DA voltage and the negative DA voltage according to the distribution voltage selection signal. The D/A converter changes the output current by differentially amplifying the selected voltage.
Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模数转换器），通过使用分压电阻而不是使用电容阵列来减少安装空间。 构成：前置放大器部分（210）包括第一和第二MOS晶体管（M1，M2）分别差分放大正输入电压和负输入电压。 数字/模拟转换器（240）包括差分放大分压器（241）的输出电压的第三和第四MOS晶体管（M3，M4）。 SAR控制单元（230）根据量化器（220）的输出位值输出用于选择正的DA电压和负的DA电压的分配电压选择信号。 量化器通过比较输出电流输出位值。 D / A转换器根据分配电压选择信号选择正的DA电压和负的DA电压。 D / A转换器通过差分放大所选择的电压来改变输出电流。
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Patent Agency Ranking6.发明公开Successive approximation register analog digital converter and operation method thereof 审中-公开连续逼近寄存器模拟数字转换器及其操作方法
公开(公告)号：KR20120060280A
公开(公告)日：2012-06-12
申请号：KR20100121449
申请日：2010-12-01
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHO YOUNG KYUN , JEON YOUNG DEUK , NAM JAE WON , KWON JONG KEE
IPC: H03M1/38
CPC classification number: H03M1/0621 , H03M1/38 , H03M2201/2233 , H03M2201/6107 , H03M2201/622
Abstract: PURPOSE: A SAR(Successive Approximation Register) ADC(Analog To Digital Converter) and an operation method thereof are provided to improve an operation speed of analog to digital conversion by optimizing latch movement. CONSTITUTION: An SAR(Successive Approximation Register) ADC(Analog To Digital Converter)(100) improves an operation speed in comparison with a general SAR ADC by using an asynchronous clock signal. The SAR ADC includes a digital conversion unit(110), an asynchronous clock generating circuit(120), and an SAR controller(130). The digital conversion unit changes an analog input voltage in response to a clock signal of the asynchronous clock generating circuit into digital signals. The asynchronous clock generating circuit generates the clock signal for controlling a sampling operation and a digital conversion operation in the digital conversion unit. The SAR controller controls the overall operation of the SAR ADC.
Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模数转换器）及其操作方法，通过优化锁存器移动来提高模数转换的操作速度。 构成：通过使用异步时钟信号，SAR（逐次逼近寄存器）ADC（模数转换器）（100）可以提高与通用SAR ADC相比的运行速度。 SAR ADC包括数字转换单元（110），异步时钟发生电路（120）和SAR控制器（130）。 数字转换单元响应于异步时钟产生电路的时钟信号将模拟输入电压改变成数字信号。 异步时钟产生电路产生用于控制数字转换单元中的采样操作和数字转换操作的时钟信号。 SAR控制器控制SAR ADC的整体运行。
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公开(公告)号：KR1020090005865A
公开(公告)日：2009-01-14
申请号：KR1020070069244
申请日：2007-07-10
Applicant: 주식회사 쎄이미지
IPC: H03M1/36
CPC classification number: H03M1/06 , H03M1/403 , H03M2201/2233 , H03M2201/615 , H03M2201/8152
Abstract: A parasitic capacitance insensitive technique for a capacitor array split circuit is provided to maintain the fixed voltage in the parasitic capacitance by setting up the charge-control part in the off switch. A complementation switched capacitor combination(30) comprises az complementary switch(31) and a capacitor(32). The complementary switch is made of an on-switch(31-1) and an off-switch(31-2). The capacitor receives the predetermined electric potential according to the on/off of the complementary switch. A charge-control part(10) is formed with the operational amplifier. The output terminal of the operational amplifier is connected to the inverted input terminal. The complementation switched capacitor combination is serially connected to the charge-control part. The complementary switch is serially connected to the capacitor. One side plate of capacitor is connected to the C+ terminal. The other side plate of capacitor is connected to one node of the complementary switch. On switch of the complementary switch is connected to the C- terminal. The off switch of the complementary switch is connected to I node.
Abstract translation: 提供了用于电容器阵列分离电路的寄生电容不灵敏技术，通过在断开开关中设置充电控制部分来将固定电压维持在寄生电容中。 互补开关电容器组合（30）包括az互补开关（31）和电容器（32）。 互补开关由开关（31-1）和断开开关（31-2）组成。 电容器根据互补开关的开/关来接收预定的电位。 电荷控制部件（10）由运算放大器形成。 运算放大器的输出端子连接到反相输入端子。 互补开关电容器组合串联连接到充电控制部分。 互补开关串联连接到电容器。 电容器的一个侧板连接到C +端子。 电容器的另一侧板连接到互补开关的一个节点。 互补开关的开关连接到C端子。 互补开关的关闭开关连接到I节点。
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公开(公告)号：KR101586407B1
公开(公告)日：2016-01-18
申请号：KR1020140137713
申请日：2014-10-13
Applicant: 광주과학기술원
CPC classification number: H03M1/1023 , H03M1/0621 , H03M1/403 , H03M2201/2233 , H03M2201/63
Abstract: 본발명의실시예는 SAR ADC의캐패시터미스매치보정방법으로서, SAR ADC에입력신호를인가하는단계, SAR ADC의캐패시터중 k번째에마련된캐패시터의웨이트값(W)을샘플링하는단계, 모든웨이트에대한에러를포함한값(V)을도출하는단계, ADC 출력값인디지털코드값의샘플간차이값을합산하여평균값을구하고상기평균값을캐패시터의웨이트값으로설정하여캐패시터의미스매치를보정하는단계를포함할수 있다. 따라서, 실시예는비교적간단한연산을통해캐패시터의미스매치보정이가능하고추가적인아날로그회로또는또 다른 ADC가구비되지않아시스템의크기를유지할수 있다.
Abstract translation: 本发明的实施例涉及一种用于校正SAR ADC中的电容器失配的方法，包括以下步骤：将输入信号施加到SAR ADC; 对配置在SAR ADC的第k个电容器中的电容器的权重值（Wk）进行采样; 提取包括所有权重错误的值（VE）; 以及通过对作为ADC输出值的数字码值的采样之间的差值求和并将该平均值设置为电容器的权重值来计算平均值来校正电容器的失配。 因此，根据本发明的实施例，可以通过相对简单的计算来校正电容器的失配; 并且可以将系统的尺寸维持为附加模拟电路或不排列另一ADC。
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公开(公告)号：KR101471611B1
公开(公告)日：2014-12-11
申请号：KR1020130085283
申请日：2013-07-19
Applicant: 전자부품연구원
IPC: H03M1/12
CPC classification number: H03M1/38 , H03M1/1205 , H03M1/1245 , H03M2201/2216 , H03M2201/2233 , H03M2201/61 , H03M2201/643
Abstract: 레퍼런스 전압 변동 방지 기법을 적용한 다채널 SAR 타입 ADC 장치 및 방법이 제공된다. 본 발명의 실시예에 따른, ADC 장치에 구비된 각각의 ADC는, 아날로그 입력 신호의 전압인 입력 전압과 레퍼런스 전압을 형성하고, 입력 전압과 레퍼런스 전압을 비교하여 디지털 데이터로 비교 결과를 출력하며, 비교 결과를 외부에 출력하기 위해 기록하고, 레퍼런스 전압 형성을 위한 연결 동작을 다른 ADC와 함께 수행한다. 이에 의해, 입력 전압과 레퍼런스 전압을 비교하는 구간에 레퍼런스가 변동하는 것을 방지하여, 비교중인 채널의 비교부에 입력되는 레퍼런스 변동에 의한 오작동을 방지할 수 있어, 고해상도 ADC를 제공할 수 있게 된다.
Abstract translation: 提供一种采用参考电压波动预防方案的多通道SAR型ADC的装置和方法。 根据本发明的实施例，ADC装置中提供的每个ADC形成作为模拟输入信号的电压的输入电压和参考电压，将输入电压与参考电压进行比较，以将比较结果输出为 数字数据记录将被外部输出的比较结果，并与另一个ADC一起执行连接操作以形成参考电压。 因此，在比较输入电压和参考电压的部分中，防止参考波动，从而可以防止输入到被比较的通道的比较单元中的参考波动的故障，因此高分辨率ADC可以 提供。
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公开(公告)号：KR1020140063059A
公开(公告)日：2014-05-27
申请号：KR1020120129957
申请日：2012-11-16
Applicant: 서강대학교산학협력단
IPC: H03M1/38
CPC classification number: H03M1/14 , H03M1/361 , H03M1/38 , H03M2201/2216 , H03M2201/2233 , H03M2201/76
Abstract: The present invention relates to a pipelined ADC. A first end thereof is configured to be formed by two SAR ADC which is provided in a dual channel and the remaining end thereof is configured to be formed by a first flash ADC and a second flash ADC which are provided in a single channel. The present invention is capable of rapid operation because a Nyquist input signal is appropriately processed even without a secure hash algorithm (SHA) and simultaneously the speed of the operation is not limited by the SAR ADC.
Abstract translation: 本发明涉及流水线ADC。 其第一端被配置成由设置在双通道中的两个SAR ADC形成，其另一端被配置为由设置在单个通道中的第一闪存ADC和第二闪存ADC形成。 本发明能够快速操作，因为即使没有安全散列算法（SHA）也适当地处理奈奎斯特输入信号，并且同时运行速度不受SAR ADC的限制。
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