公开(公告)号：KR101435978B1

公开(公告)日：2014-09-02

申请号：KR1020120129957

申请日：2012-11-16

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  황동현 ,  박준상

IPC: H03M1/38

Abstract: 본 발명은 파이프라인 ADC에 관한 것으로서 첫 번째 단은 이중채널로 구현되는 두 개의 SAR ADC로 형성되고, 나머지 단은 단일채널로 구현되는 제 1 플래쉬(flash) ADC 및 제 2 플래쉬 ADC로 형성되는 것을 특징함으로써, SHA 없이도 Nyquist의 입력신호까지 적절히 처리할 수 있음과 동시에 SAR ADC에 의해 동작 속도가 제한되지 않으므로 고속 동작이 가능하다.

公开(公告)号：KR101162719B1

公开(公告)日：2012-07-05

申请号：KR1020110049807

申请日：2011-05-25

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 황원석 ,  이승훈 ,  송정은 ,  황동현

IPC: H03M1/12

CPC classification number: H03M1/145 ,  H03F1/0261 ,  H03F3/45 ,  H03F3/45183 ,  H03M1/1225 ,  H03M1/168

Abstract: PURPOSE: An amplifying circuit and an analog digital converting circuit including the same are provided to efficiently reduce a consumable current of an analog to digital converter in a pipeline architecture by sharing the amplifying circuit. CONSTITUTION: A first amplifying circuit(240) comprises first and second rod parts(10,20), an output part(30), first and second input parts(40,50), and a first constant current source part(60). The first load part includes first to third transistors(T1-T3). The second rod parting includes fourth to sixth transistors(T4-T6). An output part includes two seventh to two tenth transistors(T7-T10) which are serially connected, respectively. The first input part includes eleventh to thirteenth transistors(T11-T13). The second input part includes fourteenth to sixteenth transistors(T14-T16). The first constant current part includes seventeenth to nineteenth transistors(T17-T19). A second amplifying circuit(250) includes third and fourth load parts(80,90), an third input part(70), and a second static current source part(95).

Abstract translation: 目的：提供一种放大电路和包括该放大电路的模拟数字转换电路，以通过共享放大电路来有效降低流水线架构中的模数转换器的消耗电流。 构成：第一放大电路（240）包括第一和第二杆部分（10,20），输出部分（30），第一和第二输入部分（40,50）和第一恒定电流源部分（60）。 第一负载部分包括第一至第三晶体管（T1-T3）。 第二棒分离包括第四至第六晶体管（T4-T6）。 输出部分分别包括串联连接的两个第七至第二十个晶体管（T7-T10）。 第一输入部包括第十一至第十三晶体管（T11-T13）。 第二输入部包括第十四至第十六晶体管（T14-T16）。 第一恒定电流部分包括第十七至第十九晶体管（T17-T19）。 第二放大电路（250）包括第三和第四负载部分（80,90），第三输入部分（70）和第二静态电流源部分（95）。

公开(公告)号：KR1020140063059A

公开(公告)日：2014-05-27

申请号：KR1020120129957

申请日：2012-11-16

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  황동현 ,  박준상

IPC: H03M1/38

CPC classification number: H03M1/14 ,  H03M1/361 ,  H03M1/38 ,  H03M2201/2216 ,  H03M2201/2233 ,  H03M2201/76

Abstract: The present invention relates to a pipelined ADC. A first end thereof is configured to be formed by two SAR ADC which is provided in a dual channel and the remaining end thereof is configured to be formed by a first flash ADC and a second flash ADC which are provided in a single channel. The present invention is capable of rapid operation because a Nyquist input signal is appropriately processed even without a secure hash algorithm (SHA) and simultaneously the speed of the operation is not limited by the SAR ADC.

Abstract translation: 本发明涉及流水线ADC。 其第一端被配置成由设置在双通道中的两个SAR ADC形成，其另一端被配置为由设置在单个通道中的第一闪存ADC和第二闪存ADC形成。 本发明能够快速操作，因为即使没有安全散列算法（SHA）也适当地处理奈奎斯特输入信号，并且同时运行速度不受SAR ADC的限制。