公开(公告)号：KR102099896B1

公开(公告)日：2020-04-13

申请号：KR1020180063433

申请日：2018-06-01

Applicant: 아주대학교산학협력단 ,  서강대학교산학협력단

Inventor： 김상완 ,  최우영

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739

公开(公告)号：KR101990806B1

公开(公告)日：2019-06-19

申请号：KR1020170144644

申请日：2017-11-01

Applicant: 서강대학교산학협력단

Inventor： 최우영

IPC: B81B7/00 ,  H01L23/485 ,  H01L25/07 ,  B81C1/00

公开(公告)号：KR101916463B1

公开(公告)日：2018-11-07

申请号：KR1020120070923

申请日：2012-06-29

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 최우영 ,  윤규한

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/66

Abstract: 본발명에따른반도체소자의안티퓨즈(anti-fuse)는기판에서로이격형성된소오스및 드레인; 일단이상기소오스에접촉하고, 타단이상기드레인에접촉하도록상기기판상에형성된게이트절연막; 및상기소오스및 드레인측의단부각각에, 게이트폭 방향으로게이트의길이가증가하다가감소하는코너부를적어도하나포함하여상기게이트절연막상에형성된게이트전극;을포함하는것을특징으로한다.

公开(公告)号：KR101870998B1

公开(公告)日：2018-06-25

申请号：KR1020120070676

申请日：2012-06-29

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 최우영 ,  윤규한

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: 절연막의파괴위치의제어가가능하고, 절연막파괴후의저항산포를개선할수 있는반도체소자의안티퓨즈및 그제조방법을개시한다. 본발명에따른반도체소자의안티퓨즈는기판에, 서로이격형성된소오스및 드레인; 일단이상기소오스에접촉하고, 타단이상기드레인에접촉하도록, 상기기판상에형성된게이트절연막; 및상기게이트절연막상에형성된게이트전극;을포함하며, 상기게이트절연막의양단중 적어도한 쪽에의두께가중앙부의두께보다얇은것을특징으로한다.

公开(公告)号：KR1020140013415A

公开(公告)日：2014-02-05

申请号：KR1020120080281

申请日：2012-07-23

Applicant: 서강대학교산학협력단

Inventor： 최우영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L41/0926 ,  H01L27/10882

Abstract: The present invention is to provide a laterally-actuated electromechanical memory device with a T cell structure and a method of fabricating the same. A right/left main word line, a bit line, and a sub word line are formed as the first conductive layer of a first layer in a horizontal direction. A right/left cantilever electrode is integrally formed in both sides of a bit line. The T cell structure can be driven between each right/left main word line and the sub word line. At least two cell strings where the laterally-actuated electromechanical memory device is arranged as a unit memory cell are stacked in a horizontal and/or vertical direction. The bit line of an upper and a lower layer and the right/left main word line are electrically and vertically connected through each contact plug while the bit line of an upper and lower layer and a line of each layer are formed.

Abstract translation: 本发明提供一种具有T单元结构的横向致动机电存储器件及其制造方法。 右/左主字线，位线和子字线形成为水平方向上的第一层的第一导电层。 左/右悬臂电极整体形成在位线的两侧。 可以在每个右/左主字线和子字线之间驱动T单元结构。 横向驱动的机电存储器件被布置为单元存储单元的至少两个单元串被堆叠在水平和/或垂直方向上。 上，下层的位线和右/左主字线通过每个接触插塞电连接并垂直连接，同时形成上层和下层的位线和各层的线。

公开(公告)号：KR101286707B1

公开(公告)日：2013-07-16

申请号：KR1020120052537

申请日：2012-05-17

Applicant: 서울대학교산학협력단 ,  서강대학교산학협력단

Inventor： 박병국 ,  김상완 ,  최우영

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7855 ,  H01L29/66931 ,  H01L29/7311 ,  H01L29/7376

Abstract: PURPOSE: A tunneling field effect transistor having the FINFET structure of an independent dual gate and a fabrication method thereof are provided to increase the driving current without the loss of a separate area by forming a vertical dual gate structure which is electrically separated from both sides of a semiconductor pin. CONSTITUTION: A semiconductor substrate (10) includes a semiconductor pin (14) at a constant height. A p+ region (62) and an n+ region (64) are formed at both sides of the semiconductor substrate. The semiconductor pin is formed between the p+ region and the n+ region. A first gate (52) is formed between one side of the semiconductor pin and the n+ region. A second gate (54) is formed between the other side of the semiconductor pin and the p+ region. The material of the first gate is different from that of the second gate.

Abstract translation: 目的：提供具有独立双栅极的FINFET结构的隧道场效应晶体管及其制造方法，以通过形成垂直双栅极结构来增加驱动电流而不损失单独的面积，所述垂直双栅极结构与 半导体引脚。 构成：半导体衬底（10）包括恒定高度的半导体管脚（14）。 在半导体衬底的两侧形成有p +区域（62）和n +区域（64）。 半导体管脚形成在p +区域和n +区域之间。 第一栅极（52）形成在半导体引脚的一侧和n +区之间。 第二栅极（54）形成在半导体管脚的另一侧和p +区域之间。 第一栅极的材料与第二栅极的材料不同。

公开(公告)号：KR1020130029599A

公开(公告)日：2013-03-25

申请号：KR1020110092954

申请日：2011-09-15

Applicant: 서강대학교산학협력단

Inventor： 최우영

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/41741 ,  H01L29/417 ,  H01L29/41725 ,  H01L29/4232

Abstract: PURPOSE: A transistor having a fixed charge layer in a buried insulating layer and a fabrication method thereof are provided to control threshold voltage by using a fixed charge layer. CONSTITUTION: A channel region(45,47) is formed between a source(42,46) and a drain region(44,48). A gate insulating layer(72,74) is formed on the channel region. A gate is formed on the gate insulating layer. A buried insulating layer(20) includes a first fixed charge layer(62,64) having a first impurity.

Abstract translation: 目的：提供一种在埋层绝缘层中具有固定电荷层的晶体管及其制造方法，以通过使用固定电荷层来控制阈值电压。 构成：在源极（42,46）和漏极区域（44,48）之间形成沟道区域（45,47）。 栅极绝缘层（72,74）形成在沟道区上。 栅极形成在栅极绝缘层上。 掩埋绝缘层（20）包括具有第一杂质的第一固定电荷层（62,64）。

公开(公告)号：KR101058370B1

公开(公告)日：2011-08-22

申请号：KR1020090078598

申请日：2009-08-25

Applicant: 서강대학교산학협력단

Inventor： 최우영

IPC: H01L29/786 ,  H01L21/336

Abstract: 본 발명은 터널링 전계효과 트랜지스터에 관한 것으로, 더욱 상세하게는 채널영역을 중심으로 일측 터널링이 일어나는 부분에는 트랩층을 형성하여 구동전류를 향상시키고, 반대편 타측에는 트랜지스터가 꺼졌을 때에 누설전류 발생을 억제할 수 있도록 저농도 도핑층을 구비함으로써, 저전력, 고에너지 효율을 구현할 수 있는 트랩을 갖는 터널링 전계효과 트랜지스터에 관한 것이다.
트랩, 저농도, LDD, 변형기판, 터널링, TFET

公开(公告)号：KR1020110040425A

公开(公告)日：2011-04-20

申请号：KR1020090097685

申请日：2009-10-14

Applicant: 서강대학교산학협력단

Inventor： 최우영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/10882

Abstract: PURPOSE: A T type electro-mechanical memory device and a method for operating and fabricating the same are provided to operate under extreme situation in which a conventional memory is not operated by sensing current through the contact of a cantilever electrode and an auxiliary line. CONSTITUTION: In a type electro-mechanical memory device and a method for operating and fabricating the same, a substrate having a certain flat plane is provided. A lower auxiliary word line(73) is formed on the substrate in an X-axis A bit line(25) is perpendicularly separated from the lower auxiliary word line. Main word lines(21,23) are insulated with the bit line. Bottom insulating layer(31A,31B) are formed in the lower part of the main word line.

Abstract translation: 目的：提供T型机电存储器件及其操作和制造方法，以在常规存储器不通过检测通过悬臂电极和辅助线的接触的电流来操作的极端情况下操作。 构成：在机电式存储装置及其制造方法中，提供具有一定平面的基板。 在X轴上的基板上形成下辅助字线（73），位线（25）与下辅助字线垂直分离。 主字线（21,23）与位线绝缘。 底部绝缘层（31A，31B）形成在主字线的下部。

公开(公告)号：KR101870999B1

公开(公告)日：2018-06-25

申请号：KR1020120070677

申请日：2012-06-29

Applicant: 에스케이하이닉스 주식회사 ,  서강대학교산학협력단

Inventor： 최우영 ,  윤규한

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: 유전율의차이를이용하여절연막의파괴위치의제어가가능하고, 절연막파괴후의저항산포를개선할수 있는반도체소자의안티퓨즈및 그제조방법을개시한다. 본발명에따른반도체소자의안티퓨즈(anti-fuse)는기판에서로이격형성된소오스및 드레인; 양단중 적어도어느한쪽에언더컷(under cut)이형성되어있으며, 일단이상기소오스에접촉하고, 타단이상기드레인에접촉하도록, 상기기판상에제1유전율을갖는물질을포함하여형성된게이트절연막; 상기제1유전율보다낮은제2유전율을갖는물질로, 상기언더컷을채우는언더컷충진부; 및상기게이트절연막및 언더컷충진부상에형성된게이트전극;을포함하는것을특징으로한다.