公开(公告)号：KR100444270B1

公开(公告)日：2004-08-12

申请号：KR1020020039146

申请日：2002-07-06

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이종덕 ,  김경록

IPC: H01L21/8244

CPC classification number: B82Y10/00 ,  H01L27/11 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/7613 ,  H01L29/78654 ,  Y10S438/962

Abstract: The present invention relates to a method for fabricating semiconductor device with negative differential conductance or transconductance. According to the present invention, a fabrication process thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate, and a tunneling device exhibiting the negative differential conductance or transconductance at room temperature can be implemented by using P+-N+ junction barriers as tunneling barriers and implanting impurity ions into a channel region so that their density is higher than the effective density of states where electrons or holes can exist thereon. Since the semiconductor device with the negative differential conductance or transconductance can be also be implemented even at room temperature, there is an advantage in that the present invention can be applied to an SRAM or a logic device using a device which can be turned on/off in response to a specific voltage.Further, according to the fabrication method of the present invention. miniaturization of the device can be easily made, and the reproducibility and the mass productivity of the process can be enhanced. Simultaneously, the gate, the source/drain and the channel regions are formed by the self-aligned process. Thus, there is another advantage in that a gate pitch can also be reduced.In addition, there is a further advantage in that the semiconductor device fabricated according to the present invention has the characteristic of a single electron transistor by using the channel region as the quantum dot and the two P+-N+ junctions as the tunneling barriers.

Abstract translation: 本发明涉及一种制造具有负微分电导或跨导的半导体器件的方法。 根据本发明，通过使用SOI（绝缘体上硅）衬底可以简化其制造工艺，并且可以通过使用P + -N +结势垒实现在室温下呈现负微分电导或跨导的隧穿器件 作为隧道势垒并将杂质离子注入到沟道区中，使得它们的密度高于其上可存在电子或空穴的状态的有效密度。 由于即使在室温下也可以实现具有负的微分电导或跨导的半导体器件，因此具有的优点是本发明可以应用于使用可以开/关的器件的SRAM或逻辑器件 以响应特定的电压。此外，根据本发明的制造方法。 可以容易地实现装置的小型化，并且可以提高该过程的再现性和批量生产率。 同时，通过自对准过程形成栅极，源极/漏极和沟道区域。 因此，还有一个优点是栅极节距也可以减小。此外，还有一个优点是根据本发明制造的半导体器件具有单个电子晶体管的特性，其中通过使用沟道区作为 量子点和两个P + -N +结作为隧道势垒。

公开(公告)号：KR1020040004916A

公开(公告)日：2004-01-16

申请号：KR1020020039146

申请日：2002-07-06

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이종덕 ,  김경록

IPC: H01L21/8244

CPC classification number: B82Y10/00 ,  H01L27/11 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/7613 ,  H01L29/78654 ,  Y10S438/962

Abstract: PURPOSE: A method for fabricating a semiconductor device with negative differential conductivity is provided to embody a tunneling device according to an applied voltage and a semiconductor device having negative differential conductivity at a room temperature by including a channel region with a high impurity density and a channel with length and width of several tens of nanometer. CONSTITUTION: A single crystalline silicon layer of a silicon-on-insulator(SOI) substrate composed of a silicon support member(31), a buried oxide layer(32) and the single crystalline silicon layer is etched to form a source region and a drain region that are isolated from each other. The channel region having a fine line width is connected to the source/drain region. Ions are implanted into the upper portion of the source region, the channel region and the drain region to implant impurities into the channel region, having a density higher than an effective density state in which electrons or holes can exist. The first insulation layer is formed on the source region, the channel region, the drain region and the buried oxide layer and is etched to form a sidewall spacer(39) on the sidewall of the source region, the channel region and the drain region. The second insulation layer is formed. A gate insulation layer is formed on the channel region. A gate material is deposited and etched to form a gate(37) of a fine line width in a direction vertical to the channel region. Impurity ions of different conductivity from that of the abovementioned ions are implanted into the source/drain region.

Abstract translation: 目的：提供一种用于制造具有负差分导电率的半导体器件的方法，以通过包括具有高杂质密度的沟道区和沟道来实现根据施加电压的隧道装置和在室温下具有负差分导电率的半导体器件 长度和宽度几十纳米。 构成：蚀刻由硅支撑构件（31），掩埋氧化物层（32）和单晶硅层构成的绝缘体上硅（SOI）衬底的单晶硅层，以形成源区和 漏极区域彼此隔离。 具有细线宽度的沟道区域连接到源极/漏极区域。 离子被注入到源极区域，沟道区域和漏极区域的上部，以将杂质植入沟道区域，其密度高于存在电子或空穴的有效密度状态。 第一绝缘层形成在源极区域，沟道区域，漏极区域和掩埋氧化物层上，并被蚀刻以在源极区域，沟道区域和漏极区域的侧壁上形成侧壁间隔物（39）。 形成第二绝缘层。 在沟道区上形成栅极绝缘层。 沉积并蚀刻栅极材料以在垂直于沟道区的方向上形成细线宽度的栅极（37）。 与上述离子的导电性不同的杂质离子注入源/漏区。