公开(公告)号：KR100866261B1

公开(公告)日：2008-10-31

申请号：KR1020070064262

申请日：2007-06-28

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  박세환 ,  박일한

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823493 ,  H01L27/11521

Abstract: A flash memory array using the same device and a method of fabricating the same are provided to solve the interference of stored bit and improve the degree of integration by using a vertical structure to fabricate a charge storage region and a region having a gate insulating layer in self-alignment. A flash memory device with a split gate over a recessed channel comprises a source/drain region(12a) on a semiconductor substrate; a recessed channel region between the source and the drain; a separation gate(50a) between the channel region and a first insulating layer; a second isolating layer formed on the separation gate; a third insulating layer formed on the both channel region, not contacted with the separation gate; a charge storage region(70a) formed on the third insulating layer; a forth insulating layer formed on the source and drain region; a program gate formed on the fourth and second insulating layer, between the charge storage region and the fifth insulating layer.

Abstract translation: 提供使用相同装置的闪存阵列及其制造方法，以解决存储的位的干扰并通过使用垂直结构来提高积分的程度来制造电荷存储区域和具有栅极绝缘层的区域 自对准。 在凹陷通道上具有分割栅极的闪速存储器件包括半导体衬底上的源极/漏极区域（12a）; 在源极和漏极之间的凹陷沟道区域; 在所述沟道区域和第一绝缘层之间的分离栅极（50a）; 形成在分离门上的第二隔离层; 形成在所述两通道区域上的不与所述分离栅接触的第三绝缘层; 形成在所述第三绝缘层上的电荷存储区域（70a） 形成在源区和漏区上的第四绝缘层; 形成在第四绝缘层和第二绝缘层之间的程序栅极，在电荷存储区域和第五绝缘层之间。