公开(公告)号：KR100414570B1

公开(公告)日：2004-01-07

申请号：KR1020000037659

申请日：2000-07-03

Applicant: 조동일

Inventor： 조동일 ,  이상우 ,  박상준

IPC: B81C1/00

CPC classification number: B81C1/0019 ,  B81C2201/0178 ,  H01L21/764

Abstract: An isolation method for a single crystalline silicon microstructure using a triple layer structure is disclosed. The method includes forming the triple layer composed of an insulation layer formed over an exposed surface of the silicon microstructure, a conductive layer formed over the entire insulation layer, and a metal layer formed over a top portion of the microstructure; and partially etching the conductive layer to form electrical isolation between parts of the microstructure. The method does not require a separate photolithography process for isolation, and can be effectively applied to microstructures having high aspect ratios and narrow trenches. Also disclosed are single crystalline silicon microstructures having a triple layer isolation structure formed using the disclosed method.

Abstract translation: 公开了一种使用三层结构的单晶硅微结构的隔离方法。 该方法包括：形成由在硅微结构的暴露表面上形成的绝缘层，在整个绝缘层上形成的导电层以及在微结构的顶部上形成的金属层构成的三层; 并且部分地蚀刻导电层以在微结构的部分之间形成电隔离。 该方法不需要单独的光刻工艺进行隔离，并且可以有效地应用于具有高纵横比和窄沟槽的微结构。 还公开了具有使用所公开的方法形成的三层隔离结构的单晶硅微结构。

公开(公告)号：KR1020020079040A

公开(公告)日：2002-10-19

申请号：KR1020010019656

申请日：2001-04-12

Applicant: 조동일

Inventor： 조동일 ,  박상준

IPC: H01L29/02

Abstract: PURPOSE: An insulation method for single crystal silicon microelectromechanical system(MEMS) using selective silicon on chip structure is provided to reduce the quantity of a buried insulation layer and control the depth and thickness of the layer as compared with that using SOI wafer. CONSTITUTION: An etching hole is patterned on the electrode formed on a silicon substrate, and then the depth of buried insulation layer is defined by Reactive Ion Etching(RIE). According to standard SBM process, a protection layer is deposited along the sidewall within a hole and the bottom line of the electrode is etched horizontally. The protection layer and etching mask are removed and insulation material is filled up in the gap between the floating electrode and the substrate. By performing another SBM process, the electrode of final product is supported by the buried insulation layer and by which, electrically insulated structure from the substrate is formed.

Abstract translation: 目的：提供使用选择性硅片结构的单晶硅微机电系统（MEMS）的绝缘方法，以减少埋层绝缘层的数量，并与使用SOI晶片相比，控制层的深度和厚度。 构成：在硅衬底上形成的电极上刻蚀蚀刻孔，然后通过反应离子蚀刻（RIE）定义掩埋绝缘层的深度。 根据标准SBM工艺，在孔内沿着侧壁沉积保护层，并且电极的底线被水平蚀刻。 去除保护层和蚀刻掩模，并且在浮动电极和衬底之间的间隙中填充绝缘材料。 通过进行另一个SBM工艺，最终产品的电极由掩埋绝缘层支撑，由此形成与基板的电绝缘结构。

公开(公告)号：KR100348177B1

公开(公告)日：2002-08-09

申请号：KR1020000001550

申请日：2000-01-13

Applicant: 조동일

Inventor： 조동일 ,  이상우 ,  박상준 ,  이상철

IPC: H01L21/76

Abstract: 본 발명에 의한 단결정 실리콘의 마이크로머시닝 기법에서의 깊은 트렌치 절연막을 이용한 절연 방법에 의하면, 깊은 트렌치를 채우는 절연막이, 단결정 실리콘 기판에 박힌 상태에서 전극의 중앙을 관통하여 전극을 지지하게 되어, 결과적으로 전극의 측면에는 절연막이 형성되지 않고, 실리콘 기판으로부터 이격된 'island' 형태의 전극을 형성할 수 있다. 따라서, 전극의 대부분이 공기에 의하여 절연되고, 다양한 구조로 형성될 수 있어서, 각속도계와 같이 전극의 배치가 복잡한 구조물을 제작하는데 유용하다. 또한, 구조물과 전극이 단일 공정으로 부유되고, 단일의 부유 공정에 의하여 형성된 구조물과 전극 표면에 금속막을 증착시키므로 금속막 증착을 위한 별도의 사진/식각 공정이 불필요한 장점이 있다.

公开(公告)号：KR100405176B1

公开(公告)日：2003-11-12

申请号：KR1020010019656

申请日：2001-04-12

Applicant: 조동일

Inventor： 조동일 ,  박상준

IPC: H01L29/02

Abstract: PURPOSE: An insulation method for single crystal silicon microelectromechanical system(MEMS) using selective silicon on chip structure is provided to reduce the quantity of a buried insulation layer and control the depth and thickness of the layer as compared with that using SOI wafer. CONSTITUTION: An etching hole is patterned on the electrode formed on a silicon substrate, and then the depth of buried insulation layer is defined by Reactive Ion Etching(RIE). According to standard SBM process, a protection layer is deposited along the sidewall within a hole and the bottom line of the electrode is etched horizontally. The protection layer and etching mask are removed and insulation material is filled up in the gap between the floating electrode and the substrate. By performing another SBM process, the electrode of final product is supported by the buried insulation layer and by which, electrically insulated structure from the substrate is formed.

Abstract translation: 目的：提供一种使用选择性硅片上结构的单晶硅微电子机械系统（MEMS）的绝缘方法，以减少埋入绝缘层的数量并控制层的深度和厚度，与使用SOI晶片的情况相比。 构成：在硅衬底上形成的电极上刻蚀刻蚀孔，然后通过反应离子刻蚀（RIE）定义埋入绝缘层的深度。 根据标准的SBM工艺，保护层沿侧壁沉积在孔内，并且电极的底部线被水平蚀刻。 去除保护层和蚀刻掩模，并将绝缘材料填充在浮动电极和衬底之间的间隙中。 通过执行另一种SBM工艺，最终产品的电极由掩埋绝缘层支撑，并且由此形成与基板的电绝缘结构。

公开(公告)号：KR1020030017003A

公开(公告)日：2003-03-03

申请号：KR1020010051103

申请日：2001-08-23

Applicant: 조동일

Inventor： 조동일 ,  이승기 ,  김종팔 ,  박상준 ,  백승준 ,  김세태 ,  구치완

IPC: H01L21/308

Abstract: PURPOSE: A method for fabricating a (100) directional GaAs beam having a rectangular cross-section is provided to obtain a floated (100) directional GaAs beam by using a (001) GaAs substrate as a structural material. CONSTITUTION: An etch mask having a (100) directional boundary is patterned by using a (001) GaAs substrate. A stepped structure is formed perpendicularly to a wall face of a structure by wet etching or dry etching. The amount of undercut corresponds to the amount of etch to the direction of depth if the wet etching is done. A wall protection layer of the fabricated structure is formed. A (100) directional beam is floated by the wet etching of the structure having the wall protection layer.

Abstract translation: 目的：提供一种用于制造具有矩形截面的（100）方向GaAs束的方法，以通过使用（001）GaAs衬底作为结构材料获得浮动（100）方向GaAs束。 构成：通过使用（001）GaAs衬底来图案化具有（100）方向边界的蚀刻掩模。 通过湿蚀刻或干蚀刻垂直于结构的壁面形成阶梯结构。 如果进行湿蚀刻，底切的量对应于对深度方向的蚀刻量。 形成制造结构的壁保护层。 通过对具有壁保护层的结构的湿式蚀刻来浮动（100）定向光束。

公开(公告)号：KR1020020004135A

公开(公告)日：2002-01-16

申请号：KR1020000037659

申请日：2000-07-03

Applicant: 조동일

Inventor： 조동일 ,  이상우 ,  박상준

IPC: B81C1/00

CPC classification number: B81C1/0019 ,  B81C2201/0178 ,  H01L21/764

Abstract: PURPOSE: A method for insulating a fine structure of a single crystalline silicon using a triple layer is provided to insulate a fine structure of a single crystalline silicon without an additional photo/etch process. CONSTITUTION: A thermal oxide layer is formed on a fine structure of single crystalline silicon by performing a thermal oxidation process. A conductive layer is insulated electrically with a single crystalline silicon substrate by the thermal oxide layer. A doped polysilicon layer is deposited on a surface of the thermal oxide layer by using an LPCVD(Low Pressure Chemical Vapor Deposition) method. An aluminium layer is deposited on an upper portion of a trench and a part of a sidewall of the trench by using a sputtering method or a deposition method. Each electrode is insulated by etching the deposited polysilicon layer and removing a part of the deposited polysilicon.

Abstract translation: 目的：提供使用三层绝缘单晶硅的精细结构的方法，以在没有额外的光刻/蚀刻工艺的情况下使单晶硅的精细结构绝缘。 构成：通过进行热氧化处理，在单晶硅的精细结构上形成热氧化层。 导电层通过热氧化层与单晶硅衬底电绝缘。 通过使用LPCVD（低压化学气相沉积）方法在热氧化物层的表面上沉积掺杂多晶硅层。 通过溅射法或沉积法将铝层沉积在沟槽的上部和沟槽的侧壁的一部分上。 通过蚀刻沉积的多晶硅层并去除一部分沉积的多晶硅来将每个电极绝缘。

公开(公告)号：KR100408761B1

公开(公告)日：2003-12-11

申请号：KR1020010051103

申请日：2001-08-23

Applicant: 조동일

Inventor： 조동일 ,  이승기 ,  김종팔 ,  박상준 ,  백승준 ,  김세태 ,  구치완

IPC: H01L21/308

Abstract: PURPOSE: A method for fabricating a (100) directional GaAs beam having a rectangular cross-section is provided to obtain a floated (100) directional GaAs beam by using a (001) GaAs substrate as a structural material. CONSTITUTION: An etch mask having a (100) directional boundary is patterned by using a (001) GaAs substrate. A stepped structure is formed perpendicularly to a wall face of a structure by wet etching or dry etching. The amount of undercut corresponds to the amount of etch to the direction of depth if the wet etching is done. A wall protection layer of the fabricated structure is formed. A (100) directional beam is floated by the wet etching of the structure having the wall protection layer.

Abstract translation: 目的：提供一种用于制造具有矩形截面的（100）定向GaAs束的方法，以通过使用（001）GaAs衬底作为结构材料来获得浮动（100）定向GaAs束。 构成：通过使用（001）GaAs衬底来图案化具有（100）定向边界的蚀刻掩模。 通过湿法蚀刻或干法蚀刻，垂直于结构的壁面形成台阶结构。 如果完成湿法蚀刻，底切量对应于深度方向上的蚀刻量。 制造的结构的壁保护层被形成。 （100）定向光束通过对具有壁保护层的结构进行湿法蚀刻而浮动。

公开(公告)号：KR1020030067847A

公开(公告)日：2003-08-19

申请号：KR1020020007326

申请日：2002-02-08

Applicant: 조동일

Inventor： 조동일 ,  이승기 ,  김종팔 ,  박상준 ,  백승준 ,  김세태 ,  구치완

IPC: H01L21/306

Abstract: PURPOSE: A method for manufacturing a GaAs semiconductor fine structure is provided to be capable of forming a floated fine structure having a rectangular beam type by using an ammonium hydroxide based etching solution. CONSTITUTION: An etching mask pattern is formed on the upper predetermined portion of a GaAs substrate(20) or a substrate with a GaAs layer. The GaAs substrate is etched to the direction as much as the first depth by carrying out a wet or dry etching process using the etching mask pattern. Then, a floated GaAs fine structure(27) having a rectangular beam type, is formed by carrying out a specific etching process at the lower portion of the etching mask pattern. At this time, the GaAs substrate is etched by using an ammonium hydroxide based etching solution of 30Wt% NH4OH: 30Wt% H2O2: H2O = 25ml: 25ml: 450ml.

Abstract translation: 目的：提供一种制造GaAs半导体精细结构的方法，其能够通过使用基于氢氧化铵的蚀刻溶液形成具有矩形束型的浮动精细结构。 构成：在GaAs衬底（20）的上部预定部分或具有GaAs层的衬底上形成蚀刻掩模图案。 通过使用蚀刻掩模图案进行湿式或干法蚀刻工艺，将砷化镓衬底蚀刻至<001>方向与第一深度一样多。 然后，通过在蚀刻掩模图案的下部进行特定的蚀刻工艺来形成具有矩形波束类型的漂浮的GaAs精细结构（27）。 此时，通过使用30Wt％NH 4 OH：30Wt％H 2 O 2 :H 2 O = 25ml:25ml:450ml的氢氧化铵基蚀刻溶液蚀刻GaAs衬底。

公开(公告)号：KR100300002B1

公开(公告)日：2001-11-22

申请号：KR1019980011519

申请日：1998-04-01

Applicant: 박상준 ,  이상우 ,  조동일

Inventor： 조동일 ,  이상우 ,  박상준

IPC: C23F1/00

Abstract: PURPOSE: A method for manufacturing a microstructure using single crystal silicon as a silicon substrate is provided. Whereby, the side face of a microstructure such as a moving beam and fixed beam can be formed vertically by a reactive ion etching process and the microstructure can be easily separated from the silicon substrate. CONSTITUTION: A single crystal silicon substrate is etched to the same depth as the thickness of a microstructure to be manufactured by a first reactive ion etching process, a protective film to the side surface of the patterned microstructure is vapor-deposited, the single crystal silicon substrate is etched in a vertical direction to a depth as long as the lower face of the microstructure is separated from the silicon substrate by a second reactive ion etching process and then the patterned microstructure is separated from the single crystal substrate using an alkali aqueous solution.

公开(公告)号：KR1020010073290A

公开(公告)日：2001-08-01

申请号：KR1020000001550

申请日：2000-01-13

Applicant: 조동일

Inventor： 조동일 ,  이상우 ,  박상준 ,  이상철

IPC: H01L21/76

CPC classification number: B81B3/0086 ,  B81B2203/0136 ,  B81B2203/0307 ,  B81B2203/04

Abstract: PURPOSE: An insulating method using a deep trench insulating film in the micro-machining technique of a single crystalline silicon is provided to insulate almost all electrodes with air by forming the electrode of an island type apart from a silicon substrate. CONSTITUTION: A trench(52) is formed on the center of an electrode(51) in single crystalline silicon substrate(50). The thickness of the trench(52) is thicker than that of the electrode(51). The trench(52) is filled with an insulating film. An etch hole(53) is formed to support the center of the electrode(51) in condition that the insulating film is fixed in the single crystalline silicon substrate(50), while separating the electrode(51) and the single crystalline silicon substrate(50). Next, an etching is performed.

Abstract translation: 目的：提供在单晶硅的微加工技术中使用深沟槽绝缘膜的绝缘方法，通过形成岛状电极与硅衬底隔离来将几乎所有电极与空气绝缘。 构成：在单晶硅衬底（50）中的电极（51）的中心形成沟槽（52）。 沟槽（52）的厚度比电极（51）的厚度厚。 沟槽（52）填充有绝缘膜。 在分离电极（51）和单晶硅衬底（50）的同时，在绝缘膜固定在单晶硅衬底（50）中的条件下，形成用于支撑电极（51）的中心的蚀刻孔（53） 50）。 接下来，进行蚀刻。