公开(公告)号：KR1020080109751A

公开(公告)日：2008-12-17

申请号：KR1020087021859

申请日：2006-03-07

Applicant: 학교법인 포항공과대학교 ,  이옥희

Inventor： 성영철 ,  연제인 ,  박상훈

IPC: C07K7/08 ,  C07K7/00

CPC classification number: C07K7/08 ,  A61K47/62 ,  C07K2319/03 ,  C12N15/87

Abstract: A novel peptide for intracellular transduction of the target material is provided to effectively transduce the target protein, vector, nucleic acid and compound into the cell by using a part of the peptide sequence of provitamin of the herring which permeates the cell membrane. The novel peptide for intracellular transduction of the target material has the amino acid sequence of the chemical formula(1) of Rn-X-R-R-R-Y-Y-Rn, wherein n is an integer from 3 to 5; R is arginine; X and Y are the amino acid excluding asparaginic acid and glutamic acid, and is represented by the SEQ ID NO:5. The intracellular transduction of the target material is performed by co-culturing and contacting the peptide with the target material selected from vector, DNA, RNA, protein, lipid and compound.

Abstract translation: 提供了用于靶材料的细胞内转导的新型肽，以通过使用渗透细胞膜的鲱鱼的前体维生素的肽序列的一部分来有效地将靶蛋白，载体，核酸和化合物转导入细胞。 用于靶材料的细胞内转导的新肽具有Rn-X-R-R-R-Y-Y-Rn的化学式（1）的氨基酸序列，其中n为3至5的整数; R是精氨酸; X和Y是不包括天冬氨酸和谷氨酸的氨基酸，由SEQ ID NO：5表示。 通过将肽与选自载体，DNA，RNA，蛋白质，脂质和化合物的靶物质共培养和接触来进行靶材料的细胞内转导。

公开(公告)号：KR1020050017914A

公开(公告)日：2005-02-23

申请号：KR1020030055460

申请日：2003-08-11

Applicant: 학교법인 포항공과대학교

Inventor： 장영찬 ,  박상훈 ,  박홍준

IPC: H03M1/00

CPC classification number: H03M1/1215 ,  H03M1/002 ,  H03M2201/62

Abstract: PURPOSE: A CMOS time interleaved flash analog/digital converter apparatus of a single input buffer is provided to reduce power consumption and offset of an input buffer. CONSTITUTION: According to the CMOS time interleaved flash analog/digital converter apparatus, an input buffer(10) shares an input buffer receiving an analog signal as one input buffer. The first 1-GS/s 4-bit flash analog/digital converters(ADC)(20-1 to 20-8) converts the analog signal provided from the input buffer into a digital signal. A multiple phase clock generator(30) provides a phase clock to the first 1-GS/s 4-bit flash ADC using a phase locked loop(PLL).

Abstract translation: 目的：提供单个输入缓冲器的CMOS时间交错闪存模拟/数字转换器装置，以减少输入缓冲器的功耗和偏移。 构成：根据CMOS时间交错闪存模拟/数字转换装置，输入缓冲器（10）将接收模拟信号的输入缓冲器共享为一个输入缓冲器。 第一个1-GS / s 4位闪存模拟/数字转换器（ADC）（20-1至20-8）将从输入缓冲器提供的模拟信号转换为数字信号。 多相时钟发生器（30）使用锁相环（PLL）向第一个1-GS / s 4位闪存ADC提供相位时钟。