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公开(公告)号：KR1019940001727B1
公开(公告)日：1994-03-05
申请号：KR1019910022462
申请日：1991-12-07
IPC: H03M13/00
Abstract: The circuit includes a noninverting device (1) and an inverting device (2) for converting the coding sinals into the inverting or noninverting signals, two n-bit counting means (3,4) for counting the inverting or noninverting signals by the clock, an oscillation means (6) for driving the clock of 2n transmitting ratio, a signal smapling clock output means (7) for ouputting the sampling clock, a delay means (5) for delaying the output signals, and a data detection means (8) for detecting the data from the sampling clock and delayed signals.
Abstract translation: 该电路包括用于将编码正弦转换为反相或同相信号的同相装置（1）和反相装置（2），用于通过时钟对反相或同相信号进行计数的两个n位计数装置（3,4） 用于驱动2n发送比的时钟的振荡装置（6），用于输出采样时钟的信号抽头时钟输出装置（7），用于延迟输出信号的延迟装置（5），以及数据检测装置（8） 用于检测来自采样时钟和延迟信号的数据。
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公开(公告)号：KR1019940000945B1
公开(公告)日：1994-02-04
申请号：KR1019910022463
申请日：1991-12-07
Applicant: 한국전자통신연구원
IPC: H03M1/66
Abstract: The device includes a level detection means (1) for removing noise, a half-wave rectifying means (2) for rectifying the output of level detection means(1), an Nth count means (3) for synchronously counting the data rates, a digital/analog conversion means (4) for converting the output into the amplitude value, a saw-tooth wave conversion means (5) for converting the output of the D/A converter into the saw-tooth wave, a critical value conversion means (6) for converting the saw-tooth wave into the square wave data, and a flip-flop means (7) for outputting the transmission data.
Abstract translation: 该装置包括用于消除噪声的电平检测装置（1），用于整流电平检测装置（1）的输出的半波整流装置（2），用于同步计数数据速率的第N计数装置（3） 用于将输出转换为振幅值的数字/模拟转换装置（4），用于将D / A转换器的输出转换成锯齿波的锯齿波转换装置（5），临界值转换装置 6），用于将锯齿波转换成方波数据，以及用于输出发送数据的触发器装置（7）。
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公开(公告)号：KR100897158B1
公开(公告)日：2009-05-14
申请号：KR1020070124227
申请日：2007-12-03
Applicant: 한국전자통신연구원
CPC classification number: H04B1/0053
Abstract: 본 발명은 다중 채널 튜닝 수신 장치 및 그 다중 채널 튜닝 방법에 관한 것으로, 광대역 신호를 수신하여 다수의 신호로 분리하고 분리한 신호 각각을 튜닝하고 결합하여 출력하는 광대역 무선 주파수(RF : Radio Frequency) 튜너; 상기 광대역 RF 튜너가 출력하는 튜닝된 신호를 디지털 신호로 변환하는 아날로그 디지털 변환기; 상기 디지털 변환기에서 디지털 변환한 신호에서 본딩된 채널만을 추출하는 채널라이져(Channelizer); 및, 상기 본딩된 채널 각각을 복조하는 다수의 복조기를 포함한다.
케이블 모뎀, 채널 본딩, ADC, RF 튜너-
公开(公告)号：KR1019930015366A
公开(公告)日：1993-07-24
申请号：KR1019910022463
申请日：1991-12-07
Applicant: 한국전자통신연구원
IPC: H03M1/66
Abstract: 본 발명은 FSK(Frequency Shift Keying)에 이용되는 복조기에 관한 것이다.
본 발명은 입력되는 FKS 수신신호를 구형파 펄스열로 변환하며 히스테리시스 특성폭을 부가시켜 복조기 자체에서 잡음 배제 특성을 갖게하는 레벨검출수단(1)과, 상기 레벨검출수단(1)의 출력단에 연결되어 입력되는 상기 레벨검출수단(1)의 출력을 반파 정류시키는 반파정류 수단(2)과, 상기 반파 정류수단(2)에 연결되어 상기 반파정류수단(2)을 통한 레벨검출수단(1)의 출력을 데이타전송시간에 동기시켜 계수하는 n진 계수수단(3)과, 상기 n진 계수수단(3)에 연결되어 상기 n진 계수수단(3)의 출력을 진폭치로 변환하는 디지탈-아날로그(D/A) 변환수단(4)과, 상기 디지탈-아날로그 변환수단(4)에 연결되어 상기 디지탈-아날로그 변환수단(4)의 출력을 텁니파로 변환시키는 톱니파 변환수단(5)과, 상기 톱니파 변환수단(5)에 연결되어 상기 톱니파 변환수단(5)의 출 력을 임계값과 비교된 구형파 데이타로 변환하는 임계값 변환수단(6), 및 상기 임계값 변환수단(6)에 연결되어 상기 임계값 변환수단(6)의 출력을 데이타 전송율에 동기시켜 원래의 전송데이타로 복원하여 출력하는 풀립플롭수단(7)으로 구성되는 것을 특징으로 한다.-
Patent Agency Ranking
公开(公告)号：KR1020090065035A
公开(公告)日：2009-06-22
申请号：KR1020070132457
申请日：2007-12-17
Applicant: 한국전자통신연구원
CPC classification number: H04L27/38 , H04L2027/003 , H04L2027/0053 , H04L2027/0067
Abstract: A method of phase detection for broadcast wave synchronization in high order QAM and apparatus thereof are provided to stabilize the acquisition of frequency using a phase detector. A method for detecting phase for broadcast wave synchronization in high order QAM comprises: a step of converting a signal received to recovery loop of broadcast wave into compensation signal information; a step of determining standard judge symbol information from the compensation signal information; a step of computing weight from the compensation signal information; a step of calculating phase error information; and a step of outputting the weight phase error information.
Abstract translation: 提供了一种用于高阶QAM中的广播波同步的相位检测方法及其装置，以使用相位检测器稳定频率采集。 一种用于检测高阶QAM中的广播波同步的相位的方法，包括：将接收到的广播波的恢复循环的信号转换为补偿信号信息; 从补偿信号信息确定标准判断符号信息的步骤; 从补偿信号信息计算权重的步骤; 计算相位误差信息的步骤; 以及输出加权相位误差信息的步骤。
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公开(公告)号：KR1020090062740A
公开(公告)日：2009-06-17
申请号：KR1020070130167
申请日：2007-12-13
Applicant: 한국전자통신연구원
IPC: H04N5/50
Abstract: A broadband frequency converting apparatus and method having a 3 stage structure are provided for a multichannel reception system to convert an analog signal for each of plural channels into a digital signal using one ADC(Analog to Digital Converter) and receive a broadband channel even in a low IF. A diplexer filter(210) divides a RF(Radio Frequency) signal into an uplink signal and a downlink signal. An up-converting block(220) produces a first IF(Intermediate Frequency) signal. A first band pass filter(230) extracts only the first IF signal. A first down-converting block(240) produces a second IF signal. A second band pass filter(250) extracts only the second IF signal. A second down-converting block(260) produces a third IF signal. A low band pass filter(270) extracts only the third IF signal.
Abstract translation: 为多通道接收系统提供具有3级结构的宽带变频装置和方法，用于使用一个ADC（模/数转换器）将多通道中的每一个的模拟信号转换为数字信号，并且即使在 低IF。 双工器滤波器（210）将RF（射频）信号划分为上行链路信号和下行链路信号。 上变频块（220）产生第一IF（中频）信号。 第一带通滤波器（230）仅提取第一IF信号。 第一下变换块（240）产生第二IF信号。 第二带通滤波器（250）仅提取第二IF信号。 第二下变频块（260）产生第三IF信号。 低通滤波器（270）仅提取第三IF信号。
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公开(公告)号：KR1019950010919B1
公开(公告)日：1995-09-25
申请号：KR1019930028326
申请日：1993-12-17
Applicant: 한국전자통신연구원
IPC: H04L7/08
Abstract: at least one shift register for storing received chip data period or a part thereof; at least one or more connecting unit for connecting pairs having the same output by shift and add characteristics of a PN code; a first exclusive OR unit comprised of N exclusive OR elements; at least one or more majority logic unit for inputting P/2 number corresponding to the same position in N bit columns as a signal input; a synchronization acquisition detecting unit for outputting N data in a logic "high" level, in the case where the N outputs of the majority logic unit correspond to the N bit columns; at least one or more latch unit for inputting the N outputs and the synchronization acquisition signal; a code generating unit for receiving the output value through the latch unit to generate a code; an one period delay unit; a second exclusive OR unit for outputting an error signal; a third exclusive OR unit for outputting a receiving signal of an error corrected communication channel; and a fourth exclusive OR unit for outputting a receiving signal of an inverse distributed communication channel.
Abstract translation: 用于存储接收到的码片数据周期的至少一个移位寄存器或其一部分; 至少一个或多个连接单元，用于通过PN码的移位和相加特性连接具有相同输出的对; 由N个异或元素组成的第一个异或单元; 至少一个或多个多数逻辑单元，用于输入对应于作为信号输入的N位列中的相同位置的P / 2号; 在大多数逻辑单元的N个输出对应于N个比特列的情况下，输出逻辑“高”电平的N个数据的同步获取检测单元; 用于输入N个输出和同步获取信号的至少一个或多个锁存单元; 代码产生单元，用于通过所述锁存单元接收所述输出值以产生代码; 一个延迟单位; 用于输出误差信号的第二异或单元; 第三异或单元，用于输出纠错通信信道的接收信号; 以及第四异或单元，用于输出反向分布式通信信道的接收信号。
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公开(公告)号：KR1019950004645B1
公开(公告)日：1995-05-03
申请号：KR1019920026134
申请日：1992-12-29
Applicant: 한국전자통신연구원
IPC: H04L7/00
Abstract: The system comprises a parallel partial correlator(21) for partially correlating received signals and PN codes in parallel to output the correlating result, an integrator(23) for integrating output of a low pass filter(22), a comparator(24) for comparing threshold with output of the integrator to output the compared result, and a synchronization controller(25) for outputting an initial synchronization identification signal if the output of the integrator(23) is bigger than threshold.
Abstract translation: 该系统包括并行部分相关器（21），用于并行地接收接收信号和PN码以输出相关结果;积分器（23），用于积分低通滤波器（22）的输出;比较器（24），用于比较 阈值与积分器的输出以输出比较结果;以及同步控制器（25），用于如果积分器（23）的输出大于阈值则输出初始同步识别信号。
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