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公开(公告)号：KR1019960012924B1
公开(公告)日：1996-09-25
申请号：KR1019940021581
申请日：1994-08-30
Applicant: 한국전자통신연구원
IPC: H03L7/16
Abstract: judging wether a next 1st. instantaneous phase is over 2 by considering a increment of 1st. phase data width and a present 1st. instantaneous phase; calculating the 2nd. instantaneous phase by accumulating the increment of the 2nd. phase data width; calculating and detecting a time to be 2 using the 1st. and 2nd. instantaneous phases; and initializing for starting next synthesizing period if a time to be 2 is detected.
Abstract translation: 判断下一个1。 通过考虑1的增量，瞬时相位超过2。 相位数据宽度和当前1。 瞬时相 计算第二。 通过累加第二次增量的瞬时相位。 相数据宽度; 使用第1次计算和检测时间为2。 和第二。 瞬时相 并且如果检测到时间为2，则用于开始下一个合成周期的初始化。
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公开(公告)号：KR1019960009421A
公开(公告)日：1996-03-22
申请号：KR1019940021581
申请日：1994-08-30
Applicant: 한국전자통신연구원
IPC: H03L7/16
Abstract: 본 발명은 디지틀 주파수 합성기에 관한 것으로, 출력에서 발생되는 주기적인 진폭왜곡과 드리프트를 체결함으로써 발생주파수대역에서 항상 일정한 출력진폭과 드리프트가 발생되지 않는 안정된 신호를 발생할 수 있도록 하는 데 그 목적이 있다.
디지틀 직접주파 합성기에서는 입력순위상값의 크기와 클럭주파수값의 관계에 따라 출력합성파형에서 주기적으로 드리프트와 진폭왜곡이 발생된다. 이는 위상어 큐물레이터의 출력에서 잔류위상이 존재할 때 주로 발생되는 것으로 해석되고 있다.
본 발명은 기존의 위상어큐믈레이터에서 입력되는 순위상데이타를 누적할 때 누적된 위상값이 2
를 초과하는 순간에 발생되는 잔류위상 성분을 제거하고 항상 0에서 2
까지를 합성할 수 있도록 제어하는 제어부(50)와 제2의 어큐뮬레이터(60)를 포함한다.
본 발명에 따르면,출력신호의 스퓨리어스와 드리프트를 제거할 수 있어 보다 정밀한 주파수를 생성할 수 있다.-
公开(公告)号：KR1019960003097B1
公开(公告)日：1996-03-04
申请号：KR1019930026132
申请日：1993-12-01
Applicant: 한국전자통신연구원
IPC: H04B14/00
Abstract: The frequency generator is for providing frequency to a FDMA/FDD transceiver by using a single frequency source. The circuit includes a first phase locked loop(PLL1) for generating an output signal according to a channel selection signal and a reference signal, a second phase locked loop(PLL2) for generating carrier signal according to output signal of the first PLL and a modulated signal, and an injection oscillator(ILO3) for generating a local oscillation signal according to output signal of the second PLL.
Abstract translation: 频率发生器用于通过使用单个频率源向FDMA / FDD收发器提供频率。 该电路包括用于根据信道选择信号和参考信号产生输出信号的第一锁相环（PLL1），用于根据第一PLL的输出信号产生载波信号的第二锁相环（PLL2） 信号和用于根据第二PLL的输出信号产生本地振荡信号的注入振荡器（ILO3）。
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Patent Agency Ranking
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公开(公告)号：KR1019950013621B1
公开(公告)日：1995-11-13
申请号：KR1019920026098
申请日：1992-12-29
Applicant: 한국전자통신연구원
IPC: H04B7/26
Abstract: a dividing unit for inputting and dividing a first clock to determine the period for measure of the speed of a mobile station from the outside; a SBS transmission load controlling unit for inputting an output of the dividing unit and the first clock, and outputting a load control signal; a SBS transmission register transmission controlling unit for inputting an output of the SBS transmission register load controlling unit and generating the control signal; a SBS storing unit for storing a supervisory bit sequence for measuring the speed of mobile station; a SBS transmission clock controlling unit for inputting a second clock at the same speed as the SBS transmission speed; a SBS transmission register for reading a value of the SBS data of the SBS storing unit according to the load control signal of the SBS transmission register load controlling unit, and transferring the control signal of the SBS transmission register transmission controlling unit and the clock of the SBS transmission clock controlling unit; a relating unit for generating a first interrupt signal by detecting the SBS from a base station when the SBS transmitted from the base station is broadcast from the mobile station; an error detecting unit for generating a second interrupt signal to inform that the speed of the SBS cannot be measured when the SBS is not broadcast during measuring the speed of the mobile station by coupling an output of the relating unit with an output of the dividing unit; a time delay measuring unit for counting a third clock inputted from the outside according to an output of the SBS transmission register transmission controlling unit until an output is generated from the relating unit from a time when the SBS is transferred from base station; and a microcomputer for writing a value of the SBS data from the SBS storing.
Abstract translation: 分割单元，用于输入和分割第一时钟以确定用于从外部测量移动台的速度的周期; SBS发送负载控制单元，用于输入分频单元和第一时钟的输出，并输出负载控制信号; SBS发送寄存器发送控制单元，用于输入SBS发送寄存器负载控制单元的输出并产生控制信号; SBS存储单元，用于存储用于测量移动台的速度的监视比特序列; SBS传输时钟控制单元，用于以与SBS传输速度相同的速度输入第二时钟; SBS发送寄存器，用于根据SBS发送寄存器负载控制单元的负载控制信号读取SBS存储单元的SBS数据的值，并传送SBS发送寄存器发送控制单元的控制信号和 SBS传输时钟控制单元; 相关单元，用于当从基站发送的SBS从移动台广播时，通过从基站检测SBS来产生第一中断信号; 一个误差检测单元，用于产生一个第二中断信号，以通过将相关单元的输出与分割单元的输出相耦合来测量移动站的速度，当SBS不被广播时，不能测量SBS的速度 ; 时间延迟测量单元，用于根据SBS发送寄存器发送控制单元的输出对来自外部输入的第三时钟进行计数，直到从SBS从基站传送的时刻起从相关单元生成输出; 以及用于从SBS存储写入SBS数据的值的微型计算机。
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公开(公告)号：KR1019950001085B1
公开(公告)日：1995-02-08
申请号：KR1019920026131
申请日：1992-12-29
Applicant: 한국전자통신연구원
IPC: H03K19/00
Abstract: The memory error dection and removal circuit provides correct data although error occurs in the overlapped memory of large telecommunication systems operating continuously. The circuit comprises three XOR gates (U1-U3) inputting three memory data and an OR gate (U7) ORing the output of XOR gates; flip-flips (U4-U6) storing fault inputs provided by users and an AND gate (U9) ANDing the negative outputs of flip-flips; an AND gate (U10) outputing the first fault signal; AND gates (U11-U13) outputting respective first fault signals; buffers outputing data from memory data
Abstract translation: 存储器错误切除和去除电路提供正确的数据，尽管在大型电信系统连续工作的重叠存储器中发生错误。 该电路包括三个输入三个存储器数据的XOR门（U1-U3）和一个或门（U7）与异或门的输出进行或运算; 存储由用户提供的故障输入的触发翻转（U4-U6）和与门（U9）的倒档翻转的负输出; 输出第一故障信号的与门（U10）; AND门（U11-U13），输出各自的第一故障信号; 缓冲区从存储器数据输出数据
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公开(公告)号：KR1019930015497A
公开(公告)日：1993-07-24
申请号：KR1019910026045
申请日：1991-12-30
Applicant: 한국전자통신연구원
IPC: H04B1/40
Abstract: 본 발명은 휴대기와 기지국간에 무선 채널을 통해 통신하는 코드리스 폰의 통신 시스템에서 착발신 중복시 통화방법에 있어서, 상기 휴대기는 착발신 중복에 의한 통화불능상태 발생시 통화 불능 상태가 발생된 소정시간 후, 호 설정시간 송출을 포기하고 착신호 유무를 검색하는 수신 상태로 전환되어 착신 우선 처리하는 것을 특징으로 한다.
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