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公开(公告)号：KR1020070025585A
公开(公告)日：2007-03-08
申请号：KR1020050081902
申请日：2005-09-02
Applicant: 한국전자통신연구원
CPC classification number: H04L25/06
Abstract: A receiving module and a receiver including the same are provided to compare/detect previous bits with the current bits of a receiving signal to restore the receiving signal to an original receiving signal, instead of sampling an absolute value of a receiving signal waveform, thereby being easily applicable to a parallel link which operates at high speed. A comparator/detector unit(100) compares/detects a difference between previous bits and the current bits of a receiving signal having a consecutive waveform. An amplifier unit(200) amplifies a difference value detected from the comparator/detector unit(100). A sampling unit(300) samples waveform of the amplified receiving signal, and outputs available data. If the difference between the previous bits and the current bits does not exist, a bypass unit(400) immediately bypasses the inputted receiving signal to the sampling unit(300).
Abstract translation: 提供接收模块和包含该接收模块的接收机，以将先前的比特与接收信号的当前比特进行比较/检测，以将接收信号恢复为原始接收信号，而不是采样接收信号波形的绝对值，从而 容易适用于高速运行的并联链路。 比较器/检测器单元（100）比较/检测具有连续波形的接收信号的先前位和当前位之间的差。 放大器单元（200）放大从比较器/检测器单元（100）检测的差值。 采样单元（300）对放大的接收信号的波形进行采样，并输出可用数据。 如果前一比特和当前比特之间的差不存在，则旁路单元（400）立即将输入的接收信号旁路到采样单元（300）。
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公开(公告)号：KR100835983B1
公开(公告)日：2008-06-09
申请号：KR1020060122393
申请日：2006-12-05
Applicant: 한국전자통신연구원
IPC: H03G3/20
CPC classification number: H03G3/3036 , H03F3/45183 , H03F3/45475 , H03F2203/45134 , H03F2203/45138 , H03F2203/45352
Abstract: An automatic gain control detector is provided to obtain a desired control voltage-gain curve, to detect output swing of a VGA(Variable Gain Amplifier), continuously and to filter radio frequency noise by using an additional circuit. First and second transistors(M10,M20) include sources and drains connected to a supply voltage and a first node commonly and are driven according to a non-inverted output voltage and an inverted output voltage. A first current source is connected between the drains and the ground of the first and second transistors in order to supply predetermined current. A third transistors(M30) includes a source and a drain connected to the supply voltage and a second node and is driven according to a predetermined voltage. A second current source is connected between the drain of the third transistor and the ground in order to supply the predetermined current. A comparator connects non-inverted and inverted inputs with the first and second nodes respectively, compares a peak voltage of the first node with a reference voltage of the second node, and outputs a control voltage of a predetermined level to a VGA shell.
Abstract translation: 提供自动增益控制检测器以获得期望的控制电压 - 增益曲线，以连续地检测VGA（可变增益放大器）的输出摆幅，并通过使用附加电路来滤波射频噪声。 第一和第二晶体管（M10，M20）包括通常连接到电源电压和第一节点的源极和漏极，并且根据非反相输出电压和反相输出电压驱动。 第一电流源连接在第一和第二晶体管的漏极和地之间，以便提供预定电流。 第三晶体管（M30）包括连接到电源电压的源极和漏极和第二节点，并且根据预定电压被驱动。 第二电流源连接在第三晶体管的漏极和地之间以便提供预定电流。 比较器分别将非反相和反相输入与第一和第二节点连接，将第一节点的峰值电压与第二节点的参考电压进行比较，并将预定电平的控制电压输出到VGA外壳。
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公开(公告)号：KR100650670B1
公开(公告)日：2006-11-29
申请号：KR1020050081900
申请日：2005-09-02
Applicant: 한국전자통신연구원
IPC: H04L27/01
Abstract: An adaptive analog equalizer and a digital signal receiver having the same are provided to have low power consumption and a low cost by processing analog data without a data converter. An adaptive analog equalizer includes an equalizing unit(600) and an adapting unit(700). The equalizing unit(600) equalizes an ISI(Intersymbol Interference). The adapting unit(700) generates an adaptive tap coefficient(c(n+1)) to correct the intersymbol interference(ISI) in a time domain based on a following equation. c(n+1)=c(n) + u x e(n) x s(n), where the c(n) denotes a tap coefficient in a time n, the u denotes a size of tap, the e(n) denotes an error signal, and the s(n) denotes a code of equalized data in the time n.
Abstract translation: 通过在没有数据转换器的情况下处理模拟数据，提供了自适应模拟均衡器和具有该自适应模拟均衡器的数字信号接收器以具有低功耗和低成本。 自适应模拟均衡器包括均衡单元（600）和适配单元（700）。 均衡单元（600）均衡ISI（码间干扰）。 自适应单元（700）基于以下等式生成自适应抽头系数（c（n + 1））以校正时域中的符号间干扰（ISI）。 其中c（n）表示时间n中的抽头系数，u表示抽头的大小，e（n）表示 一个误差信号，并且s（n）表示时间n中的均衡数据的代码。
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公开(公告)号：KR100701429B1
公开(公告)日：2007-03-30
申请号：KR1020050081902
申请日：2005-09-02
Applicant: 한국전자통신연구원
CPC classification number: H04L25/06
Abstract: 본 발명은 수신모듈 및 이를 포함한 수신기에 관한 것으로, 연속된 파형을 갖는 수신신호의 이전 비트와 현재 비트의 차이를 비교 및 검출하기 위한 비교검출수단과, 상기 비교검출수단으로부터 검출된 차이 값을 증폭하기 위한 증폭수단과, 상기 증폭수단으로부터 증폭된 수신신호의 파형을 샘플링하여 유효 데이터를 출력하기 위한 표본화수단을 포함함으로써, Gbps급의 고속으로 동작하는 병렬 링크(parallel link) 등에 용이하게 적용할 수 있을 뿐만 아니라 심볼 간 간섭(Inter Symbol Interference, ISI), 지터(timing jitter or jitter) 및 전압 잡음 등에 강인한 효과가 있다.
수신 모듈, 수신기, 병렬 링크, 심볼 간 간섭, 지터, 신호 증대
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