公开(公告)号：KR1020030049180A

公开(公告)日：2003-06-25

申请号：KR1020010079320

申请日：2001-12-14

Applicant: 한국전자통신연구원

Inventor： 최정필 ,  박윤옥 ,  이광철 ,  정진균

IPC: G06F7/44

Abstract: PURPOSE: A fixed-width multiplier applying a modified booth decoder and a multipling method thereof are provided to definitely compensate for errors of lower bits by applying a modified booth decoder to a multiplication operator. CONSTITUTION: A multiplication operator receives a booth code modified corresponding to a bit sequence of an N bit multiplier, and a bit sequence of an N bit multiplicand, and outputs each partial multiplication result. The multiplication operator calculates an error compensation bias corresponding to the lower N-1 bit multiplication result by using all the partial multiplication results used in calculating the lower N-1 bit multiplication result. The operator calculates an upper N bit multiplication result by using the partial multiplication results and the error compensation bias.

Abstract translation: 目的：提供一种应用修改后的展台解码器的固定宽度倍增器及其乘法方法，以通过将修改的展位解码器应用于乘法运算器来明确地补偿较低位的错误。 构成：乘法运算符接收对应于N比特乘法器的比特序列修改的展位代码和N位被乘数的比特序列，并输出每个部分相乘结果。 乘法运算器通过使用用于计算较低N-1位相乘结果的全部部分相乘结果来计算与较低N-1位相乘结果相对应的误差补偿偏差。 操作者通过使用部分相乘结果和误差补偿偏差来计算上位N乘法结果。

公开(公告)号：KR100430526B1

公开(公告)日：2004-05-10

申请号：KR1020010079320

申请日：2001-12-14

Applicant: 한국전자통신연구원

Inventor： 최정필 ,  박윤옥 ,  이광철 ,  정진균

IPC: G06F7/44

Abstract: PURPOSE: A fixed-width multiplier applying a modified booth decoder and a multipling method thereof are provided to definitely compensate for errors of lower bits by applying a modified booth decoder to a multiplication operator. CONSTITUTION: A multiplication operator receives a booth code modified corresponding to a bit sequence of an N bit multiplier, and a bit sequence of an N bit multiplicand, and outputs each partial multiplication result. The multiplication operator calculates an error compensation bias corresponding to the lower N-1 bit multiplication result by using all the partial multiplication results used in calculating the lower N-1 bit multiplication result. The operator calculates an upper N bit multiplication result by using the partial multiplication results and the error compensation bias.

Abstract translation: 目的：提供一种应用修改的小室解码器的固定宽度乘法器及其多重方法，以通过将修改的小室解码器应用于乘法运算符来明确地补偿较低位的误差。 构成：乘法运算器接收对应于N位乘法器的位序列和N位被乘数的位序列而修改的booth编码，并输出每个部分乘法结果。 乘法运算器通过使用在计算较低N-1位乘法结果中使用的所有部分乘法结果来计算对应于较低N-1位乘法结果的误差补偿偏差。 运算符通过使用部分相乘结果和误差补偿偏差来计算较高的N位乘法结果。