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公开(公告)号：WO2022098167A1
公开(公告)日：2022-05-12
申请号：PCT/KR2021/016064
申请日：2021-11-05
Applicant: 한국전자통신연구원
Abstract: 통신 시스템에서 릴레이 방법 및 장치가 개시된다. 제1 통신 노드의 동작 방법은, 참조 신호를 하나 이상의 후보 R 노드들로 전송하는 단계, 상기 하나 이상의 후보 R 노드들에 속하는 제1 후보 R 노드로부터 제1 RSRP의 최소값을 포함하는 제1 피드백 정보를 수신하는 단계, 상기 하나 이상의 후보 R 노드들에 속하는 제2 후보 R 노드로부터 제2 RSRP의 최소값을 포함하는 제2 피드백 정보를 수신하는 단계, 상기 제1 피드백 정보에 기초한 제1 값과 상기 제2 피드백 정보에 기초한 제2 값을 비교하는 단계, 상기 제1 값이 상기 제2 값보다 큰 경우에 상기 제1 후보 R 노드를 릴레이 동작을 수행할 R 노드로 선택하는 단계, 및 상기 R 노드를 통해 상기 제2 통신 노드와 통신을 수행하는 단계를 포함한다.
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公开(公告)号：KR101697749B1
公开(公告)日：2017-02-01
申请号：KR1020130106509
申请日：2013-09-05
Applicant: 한국전자통신연구원
Abstract: 분리형기지국시스템이개시된다. 일실시예에따른분리형기지국시스템은국사측에설치된특정무선통신방식에따른복수의디지털유닛(Digital Unit, DU), 가입자측에설치된특정무선통신방식에따른복수의라디오유닛(Radio Unit, RU), 및이 복수의디지털유닛(DU)과이 복수의라디오유닛(RU) 사이의연결관계가동적으로변경될수 있는클라우드기지국스위치(cloud base station switch)를포함한다.
Abstract translation: 公开了一种可拆卸的基站。 根据本发明实施例的可拆卸基站包括：根据安装在中心局侧的特定无线通信系统的多个数字单元（DU）; 根据安装在用户侧的特定无线通信系统的多个无线电单元（RU）; 并且使得能够动态地改变DU和RU之间的连接的云基站交换机。 （附图标记）（142）运动控制单元
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公开(公告)号：KR1020140039991A
公开(公告)日：2014-04-02
申请号：KR1020130106509
申请日：2013-09-05
Applicant: 한국전자통신연구원
CPC classification number: H04B7/2609 , H04B7/024 , H04W88/085
Abstract: A detachable base station is disclosed. The detachable base station according to an embodiment of the present invention includes: a plurality of digital units (DU) in accordance with a particular wireless communications system installed on a central office side; a plurality of radio units (RU) in accordance with a particular wireless communications system installed on a subscriber side; and a cloud base station switch enabling a connection between the DU and the RU to be dynamically changed. [Reference numerals] (142) Motion control unit
Abstract translation: 公开了一种可拆卸的基站。 根据本发明实施例的可拆卸基站包括：根据安装在中心局侧的特定无线通信系统的多个数字单元（DU）; 根据安装在用户侧的特定无线通信系统的多个无线电单元（RU）; 并且使得能够动态地改变DU和RU之间的连接的云基站交换机。 （附图标记）（142）运动控制单元
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公开(公告)号：KR100926566B1
公开(公告)日：2009-11-12
申请号：KR1020070126234
申请日：2007-12-06
CPC classification number: H04L25/067 , H04L25/03006 , H04L2025/03426
Abstract: 본 발명은 연판정값 산출 방법 및 송신 신호 검출 방법에 관한 것이다.
본 발명은 수신된 신호에 기초해 채널을 추정하고, 복수의 데이터 스트림을 재정렬한다. 그리고, 재정렬된 데이터 스트림을 이용하여 복수의 후보 벡터를 선택하고, 각 후보 벡터에 대응하는 메트릭을 산출한다. 그리고, 각 후보 벡터 별로 산출된 메트릭을 이용하여 임계치를 계산하고, 각 후보 벡터에 대응하는 메트릭 및 임계치를 이용하여 송신 신호의 각 비트에 대한 연판정값을 산출한다.
연판정값, 다중송수신, MIMO, 공간 다중화, 메트릭, 로그우도비-
5.发明公开
公开(公告)号：KR1020090063957A
公开(公告)日：2009-06-18
申请号：KR1020070131497
申请日：2007-12-14
IPC: H04L27/22
CPC classification number: H04L27/22 , H04L27/3863
Abstract: A method and a device for dividing a receiving symbol signal into bit information are provided to perform a bit division process in a two dimensions simply by dividing the PSK(Phase Shift Keying) modulated symbol into the bit information in consideration of BRGC(Bit Reflected Gray Code) characteristic by using a coordinate rotation method. A rotation angle calculator(150) calculates the rotation angle by using each absolute value about I channel and Q channel symbol signals of the receiving signal which is arranged with the interval of the phase angle on a two dimensional concentric circle. A bit information converter(170) extracts the bit information about each of the I channel or Q channel symbol signals which are rotated by using a rotation angle outputted from the rotation angle calculator. An absolute value converter(120) produces each absolute value about the values of the I channel and Q channel symbol signals of the receiving symbol. A phase angle calculator(130) produces a radian phase angle by using each absolute value about the value of I channel and Q channel outputted from the absolute value converter. A symbol arrangement value calculator(140) produces an arrangement value of the symbols comprising the I channel or Q channel symbol signals by using the radian phase angle outputted from the phase angel calculator.
Abstract translation: 提供了一种将接收符号信号分成比特信息的方法和装置，以便通过将PSK（相移键控）调制的符号分解成比特信息来考虑BRGC（比特反射灰色 代码）特性使用坐标旋转法。 旋转角度计算器（150）通过使用在二维同心圆上以相位角间隔排列的接收信号的大约I通道和Q通道符号信号的绝对值来计算旋转角度。 位信息转换器（170）提取关于通过使用从旋转角计算器输出的旋转角旋转的I通道或Q通道符号信号中的每一个的位信息。 绝对值转换器（120）产生关于接收符号的I信道和Q信道符号信号的值的每个绝对值。 相位角计算器（130）通过使用关于从绝对值转换器输出的I通道和Q通道的值的绝对值产生弧度相位角。 符号排列值计算器（140）通过使用从相位角计算器输出的弧度相位角来产生包括I通道或Q通道符号信号的符号的排列值。
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Patent Agency Ranking
公开(公告)号：KR1020090062715A
公开(公告)日：2009-06-17
申请号：KR1020070130133
申请日：2007-12-13
CPC classification number: G06F11/26
Abstract: A device for testing a modem of a wireless communication system and a method therefor are provided to test the modem which transmits/receives a plurality of signals corresponding to each wireless channel. A signal processing unit(410) controls the power of the first transmission signal. A transmission memory(420) and a reception memory(430) receive and temporarily stores the first transmission signal from the signal processing unit. According to a control signal, a wireless signal processing unit(440) receives or transmits the second received signal. A channel is formed by a plurality of antennas which the mobile station and base station include.
Abstract translation: 提供了用于测试无线通信系统的调制解调器的装置及其方法，用于测试发送/接收与每个无线信道相对应的多个信号的调制解调器。 信号处理单元（410）控制第一发送信号的功率。 发送存储器（420）和接收存储器（430）接收并临时存储来自信号处理单元的第一发送信号。 根据控制信号，无线信号处理单元（440）接收或发送第二接收信号。 信道由移动站和基站所包含的多个天线形成。
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公开(公告)号：KR100874484B1
公开(公告)日：2008-12-18
申请号：KR1020060124509
申请日：2006-12-08
IPC: H03M13/11
Abstract: A quasi-cyclic low density parity check coding method and an apparatus thereof are provided to improve a data processing speed of a high speed by shifting a parity check matrix to a bi-direction. A quasi-cyclic low density parity check coding apparatus includes an input aligning module(210), a parity check matrix input module(220), a row multiplying calculation module(230), a first calculation module(240), a second calculation module(250), and an output aligning module(260). The input aligning module receives and aligns an input bit for a coding. The parity check matrix input module provides a shift index for shifting the aligned input bit. The row multiplying calculation module shifts the input bit to a left or right side based on the shift index, and calculates a first parity part using the shifted input bit. The first calculation module calculates a coding result value for each of components of the input bit using the first parity part. The second calculation module calculates a second parity part from the coding result value calculated by the first parity part and the first calculation module. The output aligning module calculates and outputs the quasi-cyclic low density parity check coding value using the input bit, the first parity part and the second parity part.
Abstract translation: 提供准循环低密度奇偶校验编码方法及其装置，以通过将奇偶校验矩阵移位到双向来提高高速的数据处理速度。 一种准循环低密度奇偶校验编码装置，包括输入对齐模块（210），奇偶校验矩阵输入模块（220），行相乘计算模块（230），第一计算模块（240），第二计算模块 （250）和输出对齐模块（260）。 输入对齐模块接收并对齐编码的输入位。 奇偶校验矩阵输入模块提供用于移位对齐的输入位的移位索引。 行相乘计算模块基于移位索引将输入位移位到左侧或右侧，并且使用移位的输入位来计算第一奇偶校验部分。 第一计算模块使用第一奇偶校验部分计算输入比特的每个分量的编码结果值。 第二计算模块根据由第一奇偶校验部分和第一计算模块计算的编码结果值来计算第二奇偶校验部分。 输出对齐模块使用输入比特，第一奇偶校验部分和第二奇偶校验部分来计算和输出准循环低密度奇偶校验编码值。
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公开(公告)号：KR100445900B1
公开(公告)日：2004-08-25
申请号：KR1020010084440
申请日：2001-12-24
Applicant: 한국전자통신연구원
IPC: G06F17/16
Abstract: PURPOSE: A distributed arithmetic device is provided to prevent a bottleneck in a ROM output terminal when reading corresponding data in a ROM and to reduce an electric power consumption of the total hardware area by minimizing an area of the ROM using something in common of values being stored in a ROM table when an inner product between two vectors is calculated and reducing a circumference control circuit area of the ROM therefor. CONSTITUTION: A storing unit(100) stores an inner product calculation result value between the first vector and the second vector. An address generating unit(210) creates an address capable of searching the inner product result value stored in the storing unit(100) using the first vector value. An inversion unit(220) inverts an inner product calculation result value corresponded to the created address into a result value of the opposite sign, and all symmetric calculation values are included. A coefficient adding unit(230) adds a specific coefficient which is not stored in the storing unit(100), and all inner product calculation result values between the first vector and the second vector are included. A distributed arithmetic output unit multiplexes the result values from the inversion unit(220) and the coefficient adding unit(230), and creates an output value of the distributed arithmetic device.
Abstract translation: 目的：提供一种分布式算术设备，用于在读取ROM中的相应数据时防止ROM输出终端中的瓶颈，并通过使用共同的值来最小化ROM的面积来减少总硬件区域的电力消耗 当计算两个矢量之间的内积时，存储在ROM表中，并减小ROM的周长控制电路面积。 构成：存储单元（100）存储第一向量和第二向量之间的内积计算结果值。 地址生成单元（210）使用第一矢量值创建能够搜索存储在存储单元（100）中的内积结果值的地址。 反转单元（220）将与创建的地址相对应的内积计算结果值反转为反符号的结果值，并且包括所有对称计算值。 系数加法单元（230）将未存储在存储单元（100）中的特定系数相加，并且包括第一矢量和第二矢量之间的所有内积计算结果值。 分布式算术输出单元多路复用来自反转单元（220）和系数加法单元（230）的结果值，并创建分布式算术设备的输出值。
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公开(公告)号：KR1020030054829A
公开(公告)日：2003-07-02
申请号：KR1020010085260
申请日：2001-12-26
Applicant: 한국전자통신연구원
IPC: H04B1/16
CPC classification number: H04L1/0068
Abstract: PURPOSE: A variable length division device for rate matching in a mobile communication system is provided to implement a division part of processes required to determine rate matching parameters through hardware resource sharing, when designing an asynchronous terminal modem, thereby reducing size and implementing hardware as one single chip. CONSTITUTION: A selector(110) selects a smaller one of a dividend and a signal inputted from a subtracter(150). Many comparators(120) compare the signal inputted from the selector(110) with a divisor and signals received from many transferrers(130). The transferrers(130) transfer the inputted divisor one bit by one bit in parallel. Among the signals received from the comparators(120), if the signal inputted from the selector(110) is small, a controller(140) transmits the small signal to the subtracter(150). The subtracter(150) subtracts the signal received by the controller(140) from the signal received by the selector(110).
Abstract translation: 目的：提供一种移动通信系统中用于速率匹配的可变长度分割设备，用于在设计异步终端调制解调器时，通过硬件资源共享来实现确定速率匹配参数所需的处理的划分部分，从而减小大小并将硬件实现为一个 单芯片 构成：选择器（110）从减法器（150）中选择一个较小的一个除数和一个信号。 许多比较器（120）将从选择器（110）输入的信号与除数和从许多传送器（130）接收的信号进行比较。 传送器（130）将输入的除数并行地一比特地传送一位。 在从比较器（120）接收的信号中，如果从选择器（110）输入的信号较小，则控制器（140）将该小信号发送到减法器（150）。 减法器（150）从由选择器（110）接收的信号中减去由控制器（140）接收的信号。
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公开(公告)号：KR101736167B1
公开(公告)日：2017-05-17
申请号：KR1020140016152
申请日：2014-02-12
Applicant: 한국전자통신연구원
CPC classification number: H04W28/0205 , H04B1/40 , H04W88/08
Abstract: 본발명은기지국장치및 그의신호송신방법에관한것으로, 본발명에따른기지국장치는송신데이터를제1 데이터및 제2 데이터의영역으로분리하여제1 데이터영역으로부터검출된상기제1 데이터가기 송신된데이터인지확인하고그 결과에따라상기제1 데이터및 제2 데이터영역으로부터검출된상기제2 데이터중 어느하나를압축하여인터페이스를통해송신하는디지털신호처리장치, 및상기디지털신호처리장치와연결된인터페이스를통해상기제1 데이터를수신하여저장한상태에서상기디지털신호처리장치로부터상기제2 데이터가수신되면상기제1 데이터및 상기제2 데이터를중첩시켜무선전송하도록하는무선신호처리장치를포함한다.
Abstract translation: 本发明涉及一种基站装置和信号发送方法，根据本发明的基站装置是分离的传输数据发送到第一数据和所述第二数据的区域，所述第一带从数据区的第一数据存储器传输所检测的 验证数据和所述第一数据和用于发送所述第二数据的第二数字信号处理器被压缩了经由接口的一个数据区域中检测到，并根据该结果连接到数字信号处理装置的接口 通过和在状态jeojanghan以接收所述第一数据包括无线电信号处理装置，以便当由第一数据和第二数据的无线电传输重叠从数字信号处理器接收到的第二数据。
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