公开(公告)号：KR1020120033722A

公开(公告)日：2012-04-09

申请号：KR1020100095404

申请日：2010-09-30

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  김종윤 ,  정후영

IPC: H01L27/10 ,  H01L21/8229 ,  H01L21/8239

CPC classification number: G11C13/0007 ,  B82Y10/00 ,  B82Y30/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/35 ,  G11C2213/77 ,  G11C2213/80 ,  H01L29/1606 ,  H01L51/0045 ,  H01L51/0591

Abstract: PURPOSE: A graphene oxide memory device and a manufacturing method thereof are provided to prevent non-uniformity between devices while reducing the size of the device by arranging a uniform graphene oxide thin film instead of a metal nano particle layer or an organic compound structure. CONSTITUTION: An insulating film(111) is arranged on a substrate(110). A lower electrode(120) is formed on the substrate. An electron channel layer(130) is formed with a graphene oxide on the lower electrode. An upper electrode(140) is formed on the electron channel layer. A bonding layer is formed between the substrate and the lower electrode.

Abstract translation: 目的：提供石墨烯氧化物存储器件及其制造方法，以通过布置均匀的氧化烯氧化物薄膜而不是金属纳米颗粒层或有机化合物结构来减小器件的尺寸，从而防止器件之间的不均匀性。 构成：在衬底（110）上布置绝缘膜（111）。 在基板上形成下电极（120）。 电子通道层（130）在下电极上形成有氧化石墨烯。 在电子通道层上形成上电极（140）。 在基板和下电极之间形成接合层。

公开(公告)号：KR1020100072525A

公开(公告)日：2010-07-01

申请号：KR1020080130956

申请日：2008-12-22

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  정후영 ,  유인규 ,  조경익

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/165 ,  G11C13/0004

Abstract: PURPOSE: A nonvolatile memory device and a formation method thereof are provided to provide the excellent retention property by introducing a diffusion barrier layer. CONSTITUTION: Bottom electrode(110) is formed on a substrate(100). A diffusion barrier layer(120) preventing the diffusion of the space charge is formed on the bottom electrode. A charge trapping layer(130) with the space charge limiting feature is formed on the diffusion barrier layer. Upper electrode(140) is formed on the charge trapping layer. The diffusion barrier layer is composed of the oxidation aluminum or the oxidation silicon.

Abstract translation: 目的：提供非易失性存储器件及其形成方法，以通过引入扩散阻挡层来提供优异的保留性能。 构成：底部电极（110）形成在衬底（100）上。 在底部电极上形成防止空间电荷扩散的扩散阻挡层（120）。 在扩散阻挡层上形成具有空间电荷限制特征的电荷俘获层（130）。 上电极（140）形成在电荷捕获层上。 扩散阻挡层由氧化铝或氧化硅构成。

公开(公告)号：KR1020080050989A

公开(公告)日：2008-06-10

申请号：KR1020070084717

申请日：2007-08-23

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  유민기 ,  정후영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/51 ,  G11C2213/55 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/141

Abstract: A memory device of a trap-controlled space charge limit current and a manufacturing method thereof are provided to effectively control charge trap distribution in a dielectric thin film by using a diffusion barrier layer and an inner diffusion barrier layer. A diffusion barrier layer(220) for an electrode-dielectric thin film is formed on the upper surface of a bottom electrode(210). A dielectric thin film(230) is formed on the upper portion of the diffusion barrier layer, and is composed of plural layers having different charge trap density. A top electrode(240) is formed on the upper portion of the dielectric thin film. An inner diffusion barrier layer(250) for preventing shift of charge tap is formed between the layers of the dielectric thin film.

Abstract translation: 提供陷阱控制空间电荷限制电流的存储器件及其制造方法，以通过使用扩散阻挡层和内部扩散阻挡层来有效地控制电介质薄膜中的电荷陷阱分布。 用于电极 - 电介质薄膜的扩散阻挡层（220）形成在底部电极（210）的上表面上。 介电薄膜（230）形成在扩散阻挡层的上部，由具有不同电荷陷阱密度的多个层组成。 顶部电极（240）形成在电介质薄膜的上部。 在电介质薄膜的层之间形成用于防止电荷抽头移动的内扩散阻挡层（250）。

公开(公告)号：KR100913395B1

公开(公告)日：2009-08-21

申请号：KR1020070084717

申请日：2007-08-23

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  유민기 ,  정후영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/51 ,  G11C2213/55 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided is a resistance variable non-volatile memory device using a trap-controlled Space Charge Limited Current (SCLC), and a manufacturing method thereof. The memory device includes a bottom electrode; an inter-electrode dielectric thin film diffusion prevention film formed on the bottom electrode; a dielectric thin film formed on the inter-electrode dielectric thin film diffusion prevention film and having a plurality of layers with different charge trap densities; and a top electrode formed on the dielectric thin film.