公开(公告)号：KR1020030002413A

公开(公告)日：2003-01-09

申请号：KR1020010038007

申请日：2001-06-29

Applicant: 한민구 ,  남우진

Inventor： 한민구 ,  남우진 ,  이민철 ,  정상훈 ,  송인혁

IPC: G02F1/136

Abstract: PURPOSE: A method for fabricating poly crystalline thin film transistors for an LCD panel is provided to reduce the mask steps by using the slit mask for reducing the fabricating cost while keeping the panel performance characteristics. CONSTITUTION: A method for fabricating poly crystalline thin film transistors for an LCD panel includes the steps of crystallizing an active layer by Excimer laser annealing after depositing the active layer(a-Si), depositing a gate insulating film(30a,30b) and gate electrodes(40a,40b) continuously without any forming of the active layer pattern, forming photoresist film patterns of active layer by using a slit mask, etching the gate electrodes, the gate insulating film and a poly crystalline silicon thin film(20) by using the photosensitive film, etching the gate electrodes and the gate insulating film of drain and source areas by using the photoresist film patterns remaining in gate areas, doping and activating impurities to the drain and source areas, depositing an interlayer insulating film, forming drain and source contact electrodes and forming contact holes for the connection thereof, and forming ITO contact electrodes in the drain areas and data lines(50,60) for connecting the source areas and depositing metal lines for connecting separated gate lines(70).

Abstract translation: 目的：提供一种用于制造用于LCD面板的多晶薄膜晶体管的方法，以通过使用用于降低制造成本的狭缝掩模来减小掩模步骤，同时保持面板性能特性。 构成：用于制造用于LCD面板的多晶薄膜晶体管的方法包括以下步骤：在沉积有源层（a-Si）之后通过准分子激光退火结晶活性层，沉积栅极绝缘膜（30a，30b）和栅极 电极（40a，40b）连续地形成有源层图案，通过使用狭缝掩模形成有源层的光致抗蚀剂图案，通过使用栅极电极，栅极绝缘膜和多晶硅薄膜（20）蚀刻栅极电极 感光膜，通过使用残留在栅极区域中的光致抗蚀剂图案来蚀刻栅极电极和漏极和源极区域的栅极绝缘膜，将杂质掺杂并激活到漏极和源极区域，沉积层间绝缘膜，形成漏极和源极 接触电极和形成用于其连接的接触孔，以及在漏极区域中形成ITO接触电极和数据线（50,60），用于将 源极区域和沉积用于连接分离的栅极线（70）的金属线。

公开(公告)号：KR102112425B1

公开(公告)日：2020-05-19

申请号：KR1020180170544

申请日：2018-12-27

Applicant: 남우진 ,  김진혁 ,  홍영표 ,  쿠로사키 카즈오

Inventor： 남우진 ,  김진혁 ,  홍영표 ,  쿠로사키카즈오

IPC: H01B9/02 ,  H02S40/32 ,  H01B7/02 ,  H01B7/08

公开(公告)号：KR100811998B1

公开(公告)日：2008-03-10

申请号：KR1020060121693

申请日：2006-12-04

Applicant: 삼성에스디아이 주식회사 ,  재단법인서울대학교산학협력재단 ,  한민구

Inventor： 한민구 ,  남우진 ,  박중현 ,  신희선

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78645

Abstract: A thin film transistor and a flat panel display including the same are provided to reduce effectively a leakage current by reducing kink current, horizontal electric field, and band bending. A semiconductor layer having a width and a length is formed on a substrate(10). The semiconductor layer includes a source region, a first channel region(20a), a first dopoing region(20c), a second channel region, and a drain region(20e). The first width of the first channel region is different from the second width of the second channel region. A gate insulating layer is formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. The gate electrode includes a first gate electrode(40a) formed at a position facing the first channel region and a second gate electrode(40b) formed at a position facing the second channel region.

Abstract translation: 提供薄膜晶体管和包括该薄膜晶体管的平板显示器，以通过减少扭结电流，水平电场和带弯曲来有效地减少泄漏电流。 在衬底（10）上形成具有宽度和长度的半导体层。 半导体层包括源极区，第一沟道区（20a），第一掺杂区（20c），第二沟道区和漏区（20e）。 第一沟道区的第一宽度与第二沟道区的第二宽度不同。 在半导体层上形成栅极绝缘层。 在栅极绝缘层上形成栅电极。 栅电极包括形成在面向第一沟道区的位置处的第一栅电极（40a）和形成在面向第二沟道区的位置的第二栅电极（40b）。