公开(公告)号：KR1020030002413A

公开(公告)日：2003-01-09

申请号：KR1020010038007

申请日：2001-06-29

Applicant: 한민구 ,  남우진

Inventor： 한민구 ,  남우진 ,  이민철 ,  정상훈 ,  송인혁

IPC: G02F1/136

Abstract: PURPOSE: A method for fabricating poly crystalline thin film transistors for an LCD panel is provided to reduce the mask steps by using the slit mask for reducing the fabricating cost while keeping the panel performance characteristics. CONSTITUTION: A method for fabricating poly crystalline thin film transistors for an LCD panel includes the steps of crystallizing an active layer by Excimer laser annealing after depositing the active layer(a-Si), depositing a gate insulating film(30a,30b) and gate electrodes(40a,40b) continuously without any forming of the active layer pattern, forming photoresist film patterns of active layer by using a slit mask, etching the gate electrodes, the gate insulating film and a poly crystalline silicon thin film(20) by using the photosensitive film, etching the gate electrodes and the gate insulating film of drain and source areas by using the photoresist film patterns remaining in gate areas, doping and activating impurities to the drain and source areas, depositing an interlayer insulating film, forming drain and source contact electrodes and forming contact holes for the connection thereof, and forming ITO contact electrodes in the drain areas and data lines(50,60) for connecting the source areas and depositing metal lines for connecting separated gate lines(70).

Abstract translation: 目的：提供一种用于制造用于LCD面板的多晶薄膜晶体管的方法，以通过使用用于降低制造成本的狭缝掩模来减小掩模步骤，同时保持面板性能特性。 构成：用于制造用于LCD面板的多晶薄膜晶体管的方法包括以下步骤：在沉积有源层（a-Si）之后通过准分子激光退火结晶活性层，沉积栅极绝缘膜（30a，30b）和栅极 电极（40a，40b）连续地形成有源层图案，通过使用狭缝掩模形成有源层的光致抗蚀剂图案，通过使用栅极电极，栅极绝缘膜和多晶硅薄膜（20）蚀刻栅极电极 感光膜，通过使用残留在栅极区域中的光致抗蚀剂图案来蚀刻栅极电极和漏极和源极区域的栅极绝缘膜，将杂质掺杂并激活到漏极和源极区域，沉积层间绝缘膜，形成漏极和源极 接触电极和形成用于其连接的接触孔，以及在漏极区域中形成ITO接触电极和数据线（50,60），用于将 源极区域和沉积用于连接分离的栅极线（70）的金属线。

公开(公告)号：KR100811997B1

公开(公告)日：2008-03-10

申请号：KR1020060121697

申请日：2006-12-04

Applicant: 삼성에스디아이 주식회사 ,  재단법인서울대학교산학협력재단 ,  한민구

Inventor： 한민구 ,  송인혁 ,  박중현

IPC: H01L29/786

CPC classification number: H01L29/78621 ,  H01L27/1248 ,  H01L29/78606

Abstract: A thin film transistor, a method for manufacturing the same, and a flat panel display including the same are provided to form a lightly doped drain structure in a junction part between an active region and source/drain regions by using a sidewall effect. A semiconductor layer(13) includes an active region, source/drain regions, and a lightly doped region. A gate insulating layer(14) and a gate electrode(15) are overlapped on the active region. A first interlayer dielectric(16) is formed on the source/drain regions and the gate electrode. A second interlayer dielectric(17) is formed on the first interlayer dielectric and includes a contact hole for exposing a part of the source/drain regions. Source/drain electrodes(18,19) are connected through the contact hole to the source/drain regions. The amount of the first interlayer dielectric deposited on a sidewall of the gate insulating layer is larger than the amount of the first interlayer dielectric deposited on the source/drain regions.

Abstract translation: 提供薄膜晶体管，其制造方法和包括该薄膜晶体管的平板显示器，以通过使用侧壁效应在有源区域和源极/漏极区域之间的接合部分中形成轻掺杂的漏极结构。 半导体层（13）包括有源区，源极/漏极区和轻掺杂区。 栅极绝缘层（14）和栅电极（15）重叠在有源区上。 在源极/漏极区域和栅极电极上形成第一层间电介质（16）。 第二层间电介质（17）形成在第一层间电介质上，并且包括用于暴露一部分源/漏区的接触孔。 源/漏电极（18,19）通过接触孔连接到源极/漏极区域。 沉积在栅极绝缘层的侧壁上的第一层间电介质的量大于沉积在源极/漏极区上的第一层间电介质的量。