公开(公告)号：EP3255676A1

公开(公告)日：2017-12-13

申请号：EP16173688.9

申请日：2016-06-09

Applicant: ABB Schweiz AG

Inventor： Knoll, Lars ,  Minamisawa, Renato

IPC: H01L29/06 ,  H01L29/73

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/7802

Abstract: A vertical wide bandgap power semiconductor device comprises from a source side (20) to a drain side (30) a cell (6) having
a source electrode (2), a lowly n- doped drift layer (4), wherein the source electrode (2) forms a Schottky contact to the drift layer (4), a higher doped drain sided layer (5, 55) and a drain electrode (3) formed as an ohmic contact.
A gate electrode (7) is arranged on the source side (20) and comprises an electrically conductive gate layer (70) and an insulating layer (72), which insulates the gate layer (70) from the source electrode (2) and the drift layer (4). The insulating layer (72), the source electrode (2) and the drift layer (4) attach each other at an edge (74). A thickness (76) of the insulating layer (72) at the edge (74) is chosen such that a maximum electric field at the maximum rated voltage is below 5 MeV/cm in the device.

Abstract translation: 一种垂直宽带隙功率半导体器件从源侧（20）到漏侧（30）包括具有源电极（2），低n掺杂漂移层（4）的单元（6），其中源电极 （2）形成与漂移层（4），形成为欧姆接触的较高掺杂漏极侧（5,55）和漏极（3）的肖特基接触。 栅电极（7）布置在源侧（20）上并包括将栅极层（70）与源电极（2）绝缘的导电栅极层（70）和绝缘层（72） 漂移层（4）。 绝缘层（72），源电极（2）和漂移层（4）在边缘（74）处彼此附接。 在边缘（74）处的绝缘层（72）的厚度（76）被选择为使得在该装置中在最大额定电压下的最大电场低于5MeV / cm。

公开(公告)号：EP3264470A1

公开(公告)日：2018-01-03

申请号：EP16176786.8

申请日：2016-06-29

Applicant: ABB Schweiz AG

Inventor： Knoll, Lars ,  Minamisawa, Renato

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66719 ,  H01L29/66734

Abstract: The power semiconductor device according to the invention is a trench power field effect transistor, At all locations within a channel region a first local doping concentration is less than 1·10 17 cm -3 . In the base layer a second local doping concentration is at least 1·10 17 cm -3 at all locations within the base layer. In the invention a channel length L CH , fulfils the following inequation: L CH > 4 √ ε CH t CH t GI ε GI , wherein ε CH is a permittivity of the channel region, ε GI is a permittivity of the gate insulation layer, t CH is a thickness of the channel region in a direction perpendicular to an interface between the gate insulation layer and the channel region, and t GI is a thickness of the gate insulation layer in a direction perpendicular to the interface between the gate insulation layer and the channel region.

Abstract translation: 根据本发明的功率半导体器件是沟槽功率场效应晶体管。在沟道区内的所有位置处，第一局部掺杂浓度小于1·1017cm-3。 在基极层中，第二局部掺杂浓度在基极层内的所有位置都至少为1·1017cm-3。 在本发明中，沟道长度LCH满足以下不等式：其中εCH是沟道区域的介电常数，εGI是栅极绝缘层的介电常数，tCH是沟道区域在一个方向上的厚度 垂直于栅绝缘层和沟道区之间的界面，并且tGI是栅绝缘层在垂直于栅绝缘层和沟道区之间的界面的方向上的厚度。

公开(公告)号：EP3176812A1

公开(公告)日：2017-06-07

申请号：EP15197558.8

申请日：2015-12-02

Applicant: ABB Schweiz AG

Inventor： Bartolf, Holger ,  Rahimo, Munaf ,  Knoll, Lars ,  Mihaila, Andrei ,  Minamisawa, Renato

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/7395

Abstract: A wide bandgap semiconductor device is provided comprising an (n-) doped drift layer between a first main side (20) and a second main side (22). On the first main side (20), two n doped source regions (3, 3') which are laterally surrounded by p doped channel layers (4, 4') having a channel layer depth (40). A p+ doped well layer (5) having a well layer depth (50), which is at least as large as the channel layer depth (40) is arranged at the bottom of the source regions 3, 3'. A p++ doped plug (6) having a plug depth (60), which is as least as great as the well layer depth (50), and having a higher doping concentration than the well layer (5), is arranged between the two source regions (3, 3'). On the first side (12), a first main electrode (9) contacts as an ohmic contact at least the two source regions (3, 3') and the plug (6).

Abstract translation: 提供宽带隙半导体器件，其包括在第一主侧（20）和第二主侧（22）之间的（n-）掺杂漂移层。 在第一主侧（20）上，由p沟道层深度（40）的p掺杂沟道层（4,4'）横向围绕的两个n掺杂源极区（3,3'）。 具有至少与沟道层深度（40）一样大的阱层深度（50）的p +掺杂阱层（5）被布置在源极区域3,3'的底部。 具有至少与阱层深度（50）一样大的插塞深度（60）并且具有比阱层（5）更高的掺杂浓度的p ++掺杂插塞（6）被布置在两个源极 区域（3,3'）。 在第一侧（12）上，第一主电极（9）至少作为欧姆接触接触至少两个源区（3,3'）和插塞（6）。