公开(公告)号：EP3073530A1

公开(公告)日：2016-09-28

申请号：EP15160264.6

申请日：2015-03-23

Applicant: ABB Technology AG

Inventor： Lophitis, Neophythos ,  Udrea, Florin ,  Vemulapati, Umamaheswara ,  Nistor, Iulian ,  Arnold, Martin ,  Vobecky, Jan ,  Rahimo, Munaf

IPC: H01L29/74 ,  H01L29/744 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/1027 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/41716 ,  H01L29/7416 ,  H01L29/744 ,  H01L29/87

Abstract: A reverse-conducting power semiconductor is provided. It comprises a plurality of diode cells (312) and a plurality of gate commutated thyristor (GCT) cells (32). Each GCT cell (32) comprises first cathode layer (34), wherein the first cathode layer (34) of each GCT cell (32) includes at least three cathode layer regions (34a, 34b), which are separated from each other by a base layer (35), wherein in orthogonal projection onto a plane parallel to the first main side (41) each one of the cathode layer regions (34a, 34b) is strip-shaped with a length in a direction along a longitudinal axis thereof and a width (w, w') in a direction vertical to the longitudinal axis, wherein the diode cells (312) alternate with the GCT cells (32) in a lateral direction in at least a mixed part, wherein in each GCT cell (32), the width (w') of each one of the two outer cathode layer regions (34b) next to a diode cell (312) neighbouring to that GCT cell (32) is less than the width (w) of any intermediate cathode layer region (34a) between the two outer cathode layer regions (34b) in that GCT cell (32).

公开(公告)号：EP2197025B1

公开(公告)日：2011-04-27

申请号：EP08171450.3

申请日：2008-12-12

Applicant: ABB Technology AG

Inventor： Kopta, Arnost ,  Rahimo, Munaf

IPC: H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

Abstract: For manufacturing a power semiconductor device a first oxide layer (22) is produced on a first main side of a substrate (1) of a first conductivity type. Afterwards a structured gate electrode layer (3, 3') with at least one opening (31) is produced on the first main side on top of the first oxide layer (22). First dopants of the first conductivity type are implanted into the substrate (1) on the first main side using the structured gate electrode layer (3, 3') as a mask, and the first dopants are diffused into the substrate (1). Afterwards second dopants of a second conductivity type are implanted into the substrate (1) on the first main side and the second dopants are diffused into the substrate (1). After diffusing the first dopants into the substrate (1) and before implanting the second dopants into the substrate (1) the first oxide layer (22) is partially removed. The structured gate electrode layer (3, 3') is used as a mask for implanting the second dopants.

公开(公告)号：EP1672698A1

公开(公告)日：2006-06-21

申请号：EP04405775.0

申请日：2004-12-16

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Kopta, Arnost ,  Linder, Stefan

IPC: H01L29/739 ,  H01L29/08

CPC classification number: H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

Abstract: Der erfindungsgemässe Leistungshalbleiter (1), insbesondere ein IGBT umfasst eine Driftschicht (2) mit einer Dotierung eines ersten Ladungsträgertyps und eine erste Stoppschicht (3) desselben Ladungsträgertyps wie die Driftschicht (2), wobei die Dotierung der ersten Stoppschicht (3) höher ist als die Dotierung der Driftschicht (2), sowie eine Elektrode (5) eines zweiten Ladungsträgertyps. Zwischen der ersten Stoppschicht (3) und der Elektrode (5) ist eine zweite Stoppschicht (4) des ersten Ladungsträgertyps angeordnet und die zweite Stoppschicht (4) weist eine höhere Dotierung als die erste Stoppschicht (3) auf.

Abstract translation: 半导体（1）具有掺杂电荷载流子型的漂移层和具有电荷载流子类型的掺杂的停止层（3）。 层（3）的掺杂高于层（2）的掺杂。 提供另一种电荷载体型的电极（5）。 在层（3）和电极之间布置具有前一类型掺杂的阻挡层（4）。 层（4）具有比层（3）更高的掺杂。 还包括用于制造功率半导体的方法的独立权利要求。

公开(公告)号：EP3223316A1

公开(公告)日：2017-09-27

申请号：EP16162251.9

申请日：2016-03-24

Applicant: ABB Technology AG

Inventor： Mihaila, Andrei ,  Minamisawa, Renato ,  Rahimo, Munaf ,  Canales, Francisco

IPC: H01L29/78 ,  H01L29/165

CPC classification number: H01L29/7803 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/7395 ,  H01L29/7813

Abstract: A wide bandgap power semiconductor device comprises provided having at least one MOS cell (2, 2') between a first main side (10) and a second main side (15), wherein each MOS cell (2, 2') comprises a drift layer (4) of the first conductivity type, two well layers (5, 5') of a second conductivity type and two source layers (6, 6') of the first conductivity type, which are higher doped than the drift layer (4). On the first main side (10) at each MOS cell (2, 2') two gate electrodes (7, 7') are arranged, wherein an area between the two gate electrodes (7, 7') defines a source opening (20, 20'). In the at least one MOS cell (2) at the source opening (20) a hetero-junction layer (8) consisting of a polycrystalline silicon layer is arranged between the two well layers (5, 5'), wherein the hetero-junction layer (8) has a hetero-junction layer depth (80), which is at least as deep as the well layers (5, 5').

Abstract translation: 一种宽带隙功率半导体器件包括：在第一主侧（10）和第二主侧（15）之间具有至少一个MOS单元（2,2'），其中每个MOS单元（2,2'）包括漂移 （4），第二导电类型的两个阱层（5,5'）和第一导电类型的两个源极层（6,6'），其比漂移层（4）高 ）。 在每个MOS单元（2,2'）的第一主侧（10）上布置两个栅电极（7,7'），其中两个栅电极（7,7'）之间的区域限定源开口 ，20'）。 在源极开口（20）处的至少一个MOS单元（2）中，在两个阱层（5,5'）之间布置由多晶硅层组成的异质结层（8），其中异质结 层（8）具有与阱层（5,5'）至少一样深的异质结层深度（80）。

公开(公告)号：EP2360717B1

公开(公告)日：2012-03-28

申请号：EP09178466.0

申请日：2009-12-09

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Rahimo, Munaf

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/26513 ,  H01L21/268 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface (3) comprising both, partial regions (15) doped with dopants of a first conductivity type and regions (13) doped with dopants of a ssecond conductivity type on a same side of a semiconductor substrate (7) is proposed. The method comprises (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface (3) to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial regions (15) of the surface to be patterned to a first temperature of e.g. between 900 and 1000°C using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate (7) to a second temperature being lower than the first temperature, for example to a temperature below 600°C. E.g. boron may be used as a dopant of the first conductivity type and phosphorous may be used as a dopant of the second conductivity type. As ion-implanted boron and phosphorus need different temperatures for electrical activation, boron may be activated in the regions irradiated with the laser beam only whereas phosphorus may be activated in a low temperature sintering step on the entire surface (3). Accordingly, regions doped with dopants of the first and second conductivity type can be generated within the surface (3) depending on whether the dopant of the first conductivity type is locally activated in an overcompensating doping concentration using the laser beam or not.

公开(公告)号：EP2320452B1

公开(公告)日：2011-10-19

申请号：EP09175421.8

申请日：2009-11-09

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Hemmann, Kati ,  Duran, Hamit ,  Rahimo, Munaf

IPC: H01L21/329 ,  H01L29/06 ,  H01L29/32 ,  H01L29/861 ,  H01L29/36

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

公开(公告)号：EP2360717A1

公开(公告)日：2011-08-24

申请号：EP09178466.0

申请日：2009-12-09

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf , 

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/26513 ,  H01L21/268 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface (3) comprising both, partial regions (15) doped with dopants of a first conductivity type and regions (13) doped with dopants of a ssecond conductivity type on a same side of a semiconductor substrate (7) is proposed. The method comprises (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface (3) to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial regions (15) of the surface to be patterned to a first temperature of e.g. between 900 and 1000°C using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate (7) to a second temperature being lower than the first temperature, for example to a temperature below 600°C. E.g. boron may be used as a dopant of the first conductivity type and phosphorous may be used as a dopant of the second conductivity type. As ion-implanted boron and phosphorus need different temperatures for electrical activation, boron may be activated in the regions irradiated with the laser beam only whereas phosphorus may be activated in a low temperature sintering step on the entire surface (3). Accordingly, regions doped with dopants of the first and second conductivity type can be generated within the surface (3) depending on whether the dopant of the first conductivity type is locally activated in an overcompensating doping concentration using the laser beam or not.

Abstract translation: 一种用于生产检查作为RC-IGBT或BIGT具有图案化表面（3）包括两个半导体器件的方法，掺杂有掺杂有ssecond的掺杂物的第一导电类型的掺杂剂和区域（13）的部分区域（15） 在半导体基板（7）的同一侧上导电类型的提议。 该方法包括（a）注入第一导电类型的掺杂剂和注入第二导电类型的掺杂剂到表面（3）要被图案化; 通过局部加热的表面的部分区域（15）（B）局部地激活所述第一导电类型的掺杂剂被图案化以E.G.的第一温度 900和1000℃之间使用类似于在激光退火所使用的激光束; 通过加热基底和（c）激活所述第二导电类型的掺杂剂（7）的第二温度比所述第一温度低，例如低于600℃的温度下 例如 硼可以被用作第一导电类型和磷的掺杂剂可被用作第二导电类型的掺杂剂。 作为离子注入的硼和磷需要不同温度电激活，硼可以与仅鉴于磷可以在整个表面（3）上的低温烧结步骤激活的激光束照射的区域被激活。 因此，掺杂有所述第一和第二导电类型的掺杂区域可以在表面（3）根据是否所述第一导电类型的掺杂剂是在使用激光束或不过度补偿掺杂浓度局部地激活内产生。

公开(公告)号：EP2249392A2

公开(公告)日：2010-11-10

申请号：EP10154064.9

申请日：2010-02-19

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Kopta, Arnost ,  Schnell, Raffael ,  Storasta, Liutauras ,  von Arx, Christoph

IPC: H01L29/08 ,  H01L29/739 ,  H01L21/331

CPC classification number: H01L29/0834 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7397

Abstract: A reverse-conducting semiconductor device (200) with an electrically active region is provided, which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer (100). Part of the wafer (100) forms a base layer (101) with a base layer thickness (102).
A first layer (1) of a first conductivity type with at least one first region (10) and a second layer (2) of a second conductivity type with at least one second and third region (20, 22) are alternately arranged on the collector side (103). Each region has a region area with a region width (11, 21, 23) surrounded by a region border. The RC-IGBT is designed in such a way that the following geometrical rules are fulfilled:
each third region area is an area, in which any two first regions (10) have a distance bigger than two times the base layer thickness (102);
the at least one second region is that part of the second layer (2), which is not the at least one third region (22);
the at least one third region (22) is arranged in the central part of the active region in such a way that there is a minimum distance between the third region border to the active region border of at least once the base layer thickness (102);
the sum of the areas of the at least one third region (22) is between 10 and 30 % of the active region (110); and
each first region width (11) is smaller than the base layer thickness (102).

Abstract translation: 提供具有电活性区域的反向导电半导体器件（200），其包括在同一晶片（100）上的续流二极管和绝缘栅双极晶体管。 晶片（100）的一部分形成具有基底层厚度（102）的基底层（101）。 具有至少一个具有至少一个第二和第三区域（20,22）的第二导电类型的至少一个第一区域（10）和第二层（2）的第一导电类型的第一层（1）交替布置在 集电器侧（103）。 每个区域具有由区域边界包围的区域宽度（11,21,23）的区域区域。 RC-IGBT被设计成使得满足以下几何规则：每个第三区域区域是其中任何两个第一区域（10）的距离大于基底层厚度（102）的两倍的区域; 所述至少一个第二区域是所述第二层（2）的不是所述至少一个第三区域（22）的部分; 所述至少一个第三区域（22）被布置在所述有源区域的中心部分中，使得在所述第三区域边界与所述有源区域边界之间存在至少一次所述基底层厚度（102）的最小距离， ; 所述至少一个第三区域（22）的面积之和在所述有源区域（110）的10％至30％之间; 并且每个第一区域宽度（11）小于基底层厚度（102）。

公开(公告)号：EP2045844A1

公开(公告)日：2009-04-08

申请号：EP07117817.2

申请日：2007-10-03

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Vobecky, Jan ,  Janisch, Wolfgang ,  Kopta, Arnost ,  Ritchie, Frank

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device (1) with a four-layer structure comprising layers of different conductivity types and having a collector (2) on a collector side (21) and an emitter (3) on an emitter side (31), which lies opposite the collector side (21) is produced. The steps for producing the semiconductor device are performed in the following order:
- on a wafer of a first conductivity type steps for producing layers on the emitter side (31) are performed,
- then the wafer is thinned on its second side,
- then particles of the first conductivity type are applied to the wafer on the collector side (21) by implantation or deposition of the particles of the first conductivity type for forming a first buffer layer (5), the first buffer layer (5) having a first peak doping concentration (52) in a first depth (51), which is higher than the doping of the wafer,
- then particles of a second conductivity type are applied to the wafer on its second side by implantation or deposition for forming a collector layer (6), and
- then a collector metallization (7) is formed on the second side.
At any stage particles of the first conductivity type are applied to the wafer on its second side by implantation of the particles for forming a second buffer layer (8). The second buffer layer (8) has in a second depth (81) a second peak doping concentration (82), which is lower than the first peak doping concentration (52) of the first buffer layer (5), but higher than the doping of the wafer.
There is a third buffer layer (9) arranged between the first depth (51) and the second depth (81) with a minimum doping concentration (92), which is lower than the second peak doping concentration (82) of the second buffer layer (8).
At any stage after applying the particles, a thermal treatment for forming the first buffer layer (5), the second buffer layer (8) and/or the collector layer (6) is performed.

Abstract translation: 一种具有四层结构的受控穿通半导体器件（1），其包括不同导电类型的层并且在集电极侧（21）上具有集电极（2）和发射极侧（31）上的发射极（3） 产生与集电体侧（21）相对的位置。 用于制造半导体器件的步骤按照以下顺序执行： - 在用于在发射极侧（31）上产生层的第一导电类型步骤的晶片上进行，然后晶片在其第二侧变薄，然后 第一导电类型的颗粒通过注入或沉积用于形成第一缓冲层（5）的第一导电类型的颗粒而被施加到集电器侧（21）上的晶片，第一缓冲层（5）具有第一导电类型 在第一深度（51）中的峰值掺杂浓度（52）高于晶片的掺杂，然后通过用于形成集电极层的注入或沉积将第二导电类型的颗粒施加到其第二侧上的晶片 （6），然后在第二面上形成集电体金属化（7）。 在任何阶段，通过注入用于形成第二缓冲层（8）的颗粒，第一导电类型的颗粒在其第二侧施加到晶片上。 第二缓冲层（8）在第二深度（81）具有低于第一缓冲层（5）的第一峰值掺杂浓度（52）的第二峰值掺杂浓度（82），但高于掺杂 的晶片。 布置在第一深度（51）和第二深度（81）之间的第三缓冲层（9）具有最小掺杂浓度（92），其低于第二缓冲层的第二峰值掺杂浓度（82） （8）。 在施加颗粒之后的任何阶段，进行用于形成第一缓冲层（5），第二缓冲层（8）和/或集电体层（6）的热处理。

公开(公告)号：EP3012977A1

公开(公告)日：2016-04-27

申请号：EP14190277.5

申请日：2014-10-24

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Canales, Francisco ,  Minamisawa, Renato

IPC: H03K17/567 ,  H03K17/12

CPC classification number: H03K17/567 ,  H03K17/127

Abstract: A method for switching a semiconductor module (10, 10a, 10b) with a reverse conducting insulated gate bipolar transistor (12) connected in parallel to a wide band-gap MOSFET switch (14), a semiconductor module (10, 10a, 10b), and a half bridge are proposed. The method comprises the steps of determining a nominal switching time (t n ) of the semiconductor module (10, 10a, 10b) and a gate switching time (t g ), which is prior to the nominal switching (t n ) time by a predefined delay time (t d ), and applying a negative gate voltage at the gate switching time (t g ) to a gate terminal (20) of the reverse conducting insulated gate bipolar transistor (12) and to a gate terminal (38) of the wide band-gap MOSFET switch (14), such that the wide band-gap switch (14) is switched to an off-state, in which off-state an internal reverse conducting diode of the wide band-gap switch (14) is turned off, and a current through the wide band-gap switch (14) is diverted through an internal reverse conducting diode of the insulated gate bipolar transistor (12) during the predefined delay time (t d ). This way, reverse recovery losses may be reduced.

Abstract translation: 并联连接到一个宽带隙MOSFET开关（14），半导体模块的用于切换的半导体模块（10，10A，10B）具有反向方法向导通绝缘栅双极晶体管（12）（10，10A，10B） 和半桥提出了建议。 该方法包括确定挖掘的半导体模块（10，10A，10B）和一个栅极开关时间（TG）的步骤的标称切换时间（TN），所有这些是由预定义的延迟时间之前到切换标称（TN）时间 （TD），并且在栅极切换时间施加负栅极电压（TG）对反向的栅极端子（20）向导通绝缘栅双极晶体管（12）和所述宽带隙的栅极端子（38） MOSFET开关（14）检测做了宽带隙开关（14）在关闭状态切换到，在这种关断状态的内部反向导通的宽带隙开关的二极管（14）被关断，并且 通过宽带隙开关（14）的电流通过分流到内部反向期间预定延迟时间（TD）在进行绝缘栅双极晶体管（12）的二极管。 以这种方式，反向恢复损耗可以减小。