公开(公告)号：EP3142143A1

公开(公告)日：2017-03-15

申请号：EP15184786.0

申请日：2015-09-11

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Stiegler, Karlheinz ,  Dobrzynska, Jagoda ,  Bellini, Marco

IPC: H01L21/329 ,  H01L29/861 ,  H01L29/06 ,  B23K26/364 ,  H01L21/784

CPC classification number: H01L29/66128 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/8611

Abstract: A method for manufacturing a power semiconductor device having an active region and a termination region surrounding the active region is provided. For the creation of a junction termination in the termination region the following steps are performed:
(a) providing a substrate (1) of a first conductivity type having a first side (10) and a second side (15),
(b) applying a masking layer (2, 20) on the first and on the second side (10, 15),
(c) then creating a first recess (3) on the first side, and
(d) creating a second recess (4) on the second side (15), the minimum substrate thickness (12) between the first recess (3) and the second recess (4) being thick enough to provide mechanical stability for the following manufacturing steps,
(e) after step (d) applying a first dopant (50, 550) of a second conductivity type on the first side and on the second side (10, 15), wherein the first dopant is absorbed in the masking layer (2, 20),
(f) creating a first layer (5) by driving-in the first dopant in the first recess (3) and a second layer (55) by driving-in the first dopant in the second recess (4), wherein the first layer (5) and the second layer (55) form a continuous layer between the first recess (3) and the second recess (4) and
wherein in step (d) the minimum substrate thickness (12) is so small that in step (f) the first layer (5) and the second layer (55) can form the continuous layer.

Abstract translation: 提供一种制造具有有源区域和围绕有源区域的端接区域的功率半导体器件的方法。 为了在端接区域中形成接合终端，执行以下步骤：（a）提供具有第一侧面（10）和第二侧面（15）的第一导电类型的基底（1），（b）施​​加 在第一侧和第二侧（10,15）上的掩模层（2,20），（c）然后在第一侧上形成第一凹槽（3），以及（d）在第一侧面上形成第二凹部 所述第二侧面（15）中，所述第一凹部（3）和所述第二凹部（4）之间的最小基底厚度（12）足够厚以为后续制造步骤提供机械稳定性，（e）在步骤（d）施加之后 在第一侧和第二侧（10,15）上具有第二导电类型的第一掺杂剂（50,550），其中第一掺杂剂被吸收在掩模层（2,20）中，（f）产生第一 通过在所述第一凹部（3）中驱动所述第一掺杂剂并且通过在所述第二凹部（4）中驱动所述第一掺杂剂而将所述第一层（5）和所述第二层（5） 所述第一层（55）在所述第一凹部（3）和所述第二凹部（4）之间形成连续层，并且其中在步骤（d）中，所述最小基底厚度（12）如此小以至于在步骤（f）中所述第一层 5），第二层（55）可以形成连续层。

公开(公告)号：EP2320451B1

公开(公告)日：2013-02-13

申请号：EP09175419.2

申请日：2009-11-09

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Cammarata, Marta ,  Kopta, Arnost

IPC: H01L21/329 ,  H01L29/32 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L29/32 ,  H01L29/66136

公开(公告)号：EP3073530A1

公开(公告)日：2016-09-28

申请号：EP15160264.6

申请日：2015-03-23

Applicant: ABB Technology AG

Inventor： Lophitis, Neophythos ,  Udrea, Florin ,  Vemulapati, Umamaheswara ,  Nistor, Iulian ,  Arnold, Martin ,  Vobecky, Jan ,  Rahimo, Munaf

IPC: H01L29/74 ,  H01L29/744 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/1027 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/41716 ,  H01L29/7416 ,  H01L29/744 ,  H01L29/87

Abstract: A reverse-conducting power semiconductor is provided. It comprises a plurality of diode cells (312) and a plurality of gate commutated thyristor (GCT) cells (32). Each GCT cell (32) comprises first cathode layer (34), wherein the first cathode layer (34) of each GCT cell (32) includes at least three cathode layer regions (34a, 34b), which are separated from each other by a base layer (35), wherein in orthogonal projection onto a plane parallel to the first main side (41) each one of the cathode layer regions (34a, 34b) is strip-shaped with a length in a direction along a longitudinal axis thereof and a width (w, w') in a direction vertical to the longitudinal axis, wherein the diode cells (312) alternate with the GCT cells (32) in a lateral direction in at least a mixed part, wherein in each GCT cell (32), the width (w') of each one of the two outer cathode layer regions (34b) next to a diode cell (312) neighbouring to that GCT cell (32) is less than the width (w) of any intermediate cathode layer region (34a) between the two outer cathode layer regions (34b) in that GCT cell (32).

公开(公告)号：EP2717314A1

公开(公告)日：2014-04-09

申请号：EP12187107.3

申请日：2012-10-03

Applicant: ABB Technology AG

Inventor： Botan, Virgiliu ,  Vobecky, Jan

IPC: H01L29/06 ,  H01L29/74 ,  H01L21/332 ,  H01L21/306

CPC classification number: H01L29/0661 ,  H01L21/30608 ,  H01L29/66363 ,  H01L29/74

Abstract: A method of producing a junction termination (16) for a power semiconductor device, said junction termination (16) being formed as a recess (20) at an edge of a first side of a semiconductor wafer (19) having a first region (12) of a first conductivity type (p) at said first side, said method comprising creating a second region (21) of a second, different conductivity type (n) at said edge of the first side, and removing said second region (21) using an etching fluid, e.g. a KOH solution, which provides a higher etching rate in the second region (21) than in the first region (12), so that the recess (20) is formed. The second region (21) may have a laterally varying doping (VLD) profile to obtain a recess (20) with correspondingly varying depth, e.g. a negative bevel junction termination. With a constant doping profile of the second region (21) a mesa junction termination is achieved.

Abstract translation: 对于功率半导体器件制造结终端（16）的方法，所述结终端（16）被形成为在凹部（20）在一个半导体晶片的第一侧面（19）具有第一区域的边缘（12 ）第一导电类型（p）在所述第一侧的，所述方法包括在所述第一侧的所述边缘创建不同的第二导电类型（n）的第二区域（21）;以及去除所述第二区域（21） 使用蚀刻液，例如 KOH溶液，它提供了比在第一区域（12）的第二区域（21）更高的蚀刻速率，所以DASS模具凹槽（20）形成。 所述第二区域（21）可以具有一个晚的反弹变化的掺杂（VLD）简档以获得凹部（20）具有相应变化的深度，E.G. 一个负斜角结终端。 与所述第二区域的恒定掺杂分布（21）的台面结终端实现。

公开(公告)号：EP2360717B1

公开(公告)日：2012-03-28

申请号：EP09178466.0

申请日：2009-12-09

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Rahimo, Munaf

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/26513 ,  H01L21/268 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface (3) comprising both, partial regions (15) doped with dopants of a first conductivity type and regions (13) doped with dopants of a ssecond conductivity type on a same side of a semiconductor substrate (7) is proposed. The method comprises (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface (3) to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial regions (15) of the surface to be patterned to a first temperature of e.g. between 900 and 1000°C using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate (7) to a second temperature being lower than the first temperature, for example to a temperature below 600°C. E.g. boron may be used as a dopant of the first conductivity type and phosphorous may be used as a dopant of the second conductivity type. As ion-implanted boron and phosphorus need different temperatures for electrical activation, boron may be activated in the regions irradiated with the laser beam only whereas phosphorus may be activated in a low temperature sintering step on the entire surface (3). Accordingly, regions doped with dopants of the first and second conductivity type can be generated within the surface (3) depending on whether the dopant of the first conductivity type is locally activated in an overcompensating doping concentration using the laser beam or not.

公开(公告)号：EP2320452B1

公开(公告)日：2011-10-19

申请号：EP09175421.8

申请日：2009-11-09

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Hemmann, Kati ,  Duran, Hamit ,  Rahimo, Munaf

IPC: H01L21/329 ,  H01L29/06 ,  H01L29/32 ,  H01L29/861 ,  H01L29/36

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

公开(公告)号：EP2045844A1

公开(公告)日：2009-04-08

申请号：EP07117817.2

申请日：2007-10-03

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Vobecky, Jan ,  Janisch, Wolfgang ,  Kopta, Arnost ,  Ritchie, Frank

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device (1) with a four-layer structure comprising layers of different conductivity types and having a collector (2) on a collector side (21) and an emitter (3) on an emitter side (31), which lies opposite the collector side (21) is produced. The steps for producing the semiconductor device are performed in the following order:
- on a wafer of a first conductivity type steps for producing layers on the emitter side (31) are performed,
- then the wafer is thinned on its second side,
- then particles of the first conductivity type are applied to the wafer on the collector side (21) by implantation or deposition of the particles of the first conductivity type for forming a first buffer layer (5), the first buffer layer (5) having a first peak doping concentration (52) in a first depth (51), which is higher than the doping of the wafer,
- then particles of a second conductivity type are applied to the wafer on its second side by implantation or deposition for forming a collector layer (6), and
- then a collector metallization (7) is formed on the second side.
At any stage particles of the first conductivity type are applied to the wafer on its second side by implantation of the particles for forming a second buffer layer (8). The second buffer layer (8) has in a second depth (81) a second peak doping concentration (82), which is lower than the first peak doping concentration (52) of the first buffer layer (5), but higher than the doping of the wafer.
There is a third buffer layer (9) arranged between the first depth (51) and the second depth (81) with a minimum doping concentration (92), which is lower than the second peak doping concentration (82) of the second buffer layer (8).
At any stage after applying the particles, a thermal treatment for forming the first buffer layer (5), the second buffer layer (8) and/or the collector layer (6) is performed.

Abstract translation: 一种具有四层结构的受控穿通半导体器件（1），其包括不同导电类型的层并且在集电极侧（21）上具有集电极（2）和发射极侧（31）上的发射极（3） 产生与集电体侧（21）相对的位置。 用于制造半导体器件的步骤按照以下顺序执行： - 在用于在发射极侧（31）上产生层的第一导电类型步骤的晶片上进行，然后晶片在其第二侧变薄，然后 第一导电类型的颗粒通过注入或沉积用于形成第一缓冲层（5）的第一导电类型的颗粒而被施加到集电器侧（21）上的晶片，第一缓冲层（5）具有第一导电类型 在第一深度（51）中的峰值掺杂浓度（52）高于晶片的掺杂，然后通过用于形成集电极层的注入或沉积将第二导电类型的颗粒施加到其第二侧上的晶片 （6），然后在第二面上形成集电体金属化（7）。 在任何阶段，通过注入用于形成第二缓冲层（8）的颗粒，第一导电类型的颗粒在其第二侧施加到晶片上。 第二缓冲层（8）在第二深度（81）具有低于第一缓冲层（5）的第一峰值掺杂浓度（52）的第二峰值掺杂浓度（82），但高于掺杂 的晶片。 布置在第一深度（51）和第二深度（81）之间的第三缓冲层（9）具有最小掺杂浓度（92），其低于第二缓冲层的第二峰值掺杂浓度（82） （8）。 在施加颗粒之后的任何阶段，进行用于形成第一缓冲层（5），第二缓冲层（8）和/或集电体层（6）的热处理。

公开(公告)号：EP2960941A1

公开(公告)日：2015-12-30

申请号：EP14174099.3

申请日：2014-06-26

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Arnold, Martin ,  Vobecky, Jan ,  Vemulapati, Umamaheswara

IPC: H01L29/74 ,  H01L29/744

CPC classification number: H01L29/7416 ,  H01L27/0664 ,  H01L29/744

Abstract: A reverse-conducting power semiconductor device (1) with a wafer (10) having a first main side (11) and a second main side (15), which is arranged parallel to the first main side (11), is provided. The device comprises a plurality of diode cells (96) and a plurality of GCT cells (91), wherein each GCT cell comprises layers in the following order between the first and second main side (11, 15):
- a thyristor cathode electrode (2),
- a thyristor cathode layer (4) of the first conductivity type,
- a thyristor base layer (6) of the second conductivity type,
- a drift layer (3) of the first conductivity type,
- a thyristor buffer layer (8) of the first conductivity type,
- a thyristor anode layer (5) of the second conductivity type, and
- a thyristor anode electrode (25).
Each GCT cell (91) further comprises a gate electrode (7), which is arranged lateral to the thyristor cathode layer (4) and separated from it by the thyristor base layer (6). Each diode cell (96) comprises a diode anode electrode (28) on the first main side (11), which is in contact to a diode anode layer (55) of the second conductivity type, which diode anode layer (55) is separated from the thyristor base layer (6) by the drift layer (3), a diode drift layer 3", a diode cathode layer (45) of the first conductivity type on the second main side (15), which is arranged alternating to the thyristor anode layer (5), and a diode cathode electrode. The device comprises at least one mixed part (99), in which the diode anode layers (55) of the diode cells (96) alternate with the first cathode layers (4) of the GCT cells (91).
In each diode cell (96) a diode buffer layer (32) of the first conductivity type is arranged between the diode anode layer (55) and the drift layer (3) such that the diode buffer layer (32) covers lateral sides of the diode anode layer (55) from the first main side (11) at least to a depth of 90 % of the thickness of the diode anode layer (55).

Abstract translation: 提供了具有与第一主侧（11）平行布置的具有第一主侧（11）和第二主侧（15）的晶片（10）的反向导电功率半导体装置（1）。 该装置包括多个二极管单元（96）和多个GCT单元（91），其中每个GCT单元包括在第一和第二主侧（11,15）之间的以下顺序的层： - 晶闸管阴极 2）， - 第一导电类型的晶闸管阴极层（4）， - 第二导电类型的晶闸管基极层（6）， - 第一导电类型的漂移层（3）， - 晶闸管缓冲层 8）， - 第二导电类型的晶闸管阳极层（5）和 - 可控硅阳极（25）。 每个GCT单元（91）还包括栅极电极（7），其被布置在晶闸管阴极层（4）的侧面并且由晶闸管基极层（6）与其分离。 每个二极管单元（96）包括与第二导电类型的二极管阳极层（55）接触的第一主侧（11）上的二极管阳极电极（28），该二极管阳极层（55）被分离 从晶闸管基极层（6）通过漂移层（3），二极管漂移层3“，第二导电类型的二极管阴极层（45）在第二主侧（15）上交替布置 晶闸管阳极层（5）和二极管阴极电极，该装置包括至少一个混合部分（99），其中二极管单元（96）的二极管阳极层（55）与第一阴极层（4）交替， 在每个二极管单元（96）中，第二导电类型的二极管缓冲层（32）布置在二极管阳极层（55）和漂移层（3）之间，使得二极管缓冲层 （32）从第一主侧（11）覆盖二极管阳极层（55）的横向至少至二极管阳极层（55）的厚度的90％的深度 ）。

公开(公告)号：EP2637210A1

公开(公告)日：2013-09-11

申请号：EP12158043.5

申请日：2012-03-05

Applicant: ABB Technology AG

Inventor： Rahimo, Munaf ,  Corvasce, Chiara ,  Vobecky, Jan ,  Otani, Yoichi

IPC: H01L29/08 ,  H01L29/45 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L29/66325 ,  H01L21/2251 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0834 ,  H01L29/45 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8613

Abstract: A method for manufacturing a power semiconductor device is provided comprising the following steps:
- providing a wafer (1) of a first conductivity type, which wafer has a first main side (11) and a second main side (15) opposite to the first main side (11),
- applying on the second main side (15) at least one of a dopant of the first conductivity type for forming a layer (2) of the first conductivity type and a dopant of a second conductivity type for forming a layer (2) of the second conductivity type,
- afterwards depositing a metal deposition layer (3) with a metal having a melting point above 1300 °C on the second main side (15),
- annealing the metal deposition layer (3) so that simultaneously an intermetal compound layer (35) is formed at the interface between the metal deposition layer (3) and the wafer (1) and the dopant is diffused into the wafer (1),
- creating a first metal electrode layer (4) on the second side (15).

Abstract translation: 提供了一种用于制造功率半导体器件的方法，包括以下步骤： - 提供第一导电类型的晶片（1），该晶片具有第一主侧（11）和与第一导电类型相反的第二主侧（15） 主侧（11）， - 在第二主侧（15）上施加第一导电类型的掺杂剂中的至少一种，用于形成第一导电类型的层（2）和用于形成第一导电类型的第二导电类型的掺杂剂 第二导电类型的层（2），然后在第二主侧（15）上沉积具有高于1300℃的熔点的金属的金属沉积层（3）， - 使金属沉积层（3）退火 同时在金属沉积层（3）和晶片（1）之间的界面处形成金属间化合物层（35），并且掺杂剂扩散到晶片（1）中，产生第一金属电极层（4） 在第二面（15）。

公开(公告)号：EP2320452A1

公开(公告)日：2011-05-11

申请号：EP09175421.8

申请日：2009-11-09

Applicant: ABB Technology AG

Inventor： Vobecky, Jan ,  Hemmann, Kati ,  Duran, Hamit ,  Rahimo, Munaf

IPC: H01L21/329 ,  H01L29/06 ,  H01L29/32 ,  H01L29/861 ,  H01L29/36

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

Abstract: A fast recovery diode (1) is provided, which comprises an n doped base layer (2) with a cathode side (21) and an anode side (22) opposite the cathode side (21), a p doped anode layer (5) on the anode side (22). The anode layer (5) having a doping profile comprises at least two sublayers (51, 52, 53), wherein a first sublayer (51) has a first maximum doping concentration (515), which is between 2 * 10 16 cm -3 and 2 * 10 17 cm -3 and which is higher than the maximum doping concentration of any other sublayer (52, 53). A last sublayer (52) has a last sublayer depth (520), which is larger than any other sublayer depth (51, 53), wherein the last sublayer depth (520) is between 90 to 120 µm. The doping profile of the anode layer declines such that a doping concentration in a range of 5 * 10 14 cm -3 and 1 * 10 15 cm -3 is reached between a first depth (54), which is at least 20 µm, and a second depth (55), which is at maximum 50 µm. Such a profile of the doping concentration is achieved by using aluminium diffused layers as the at least two sublayers (51, 52, 53).

Abstract translation: 提供一种快速恢复二极管（1），其包括具有阴极侧（21）的n掺杂的基底层（2）和与阴极侧（21）相对的阳极侧（22） 阳极侧（22）。 具有掺杂分布的阳极层（5）包括至少两个子层（51,52,53），其中第一子层（51）具有第一最大掺杂浓度（515），其在2×10 16 cm -3 和2×10 17 cm -3，并且高于任何其它子层（52,53）的最大掺杂浓度。 最后一个子层（52）具有比任何其它子层深度（51,53）大的最后一个子层深度（520），其中最后一个子层深度（520）在90至120μm之间。 阳极层的掺杂分布下降，使得在至少20μm的第一深度（54）和至少20μm之间达到在5×10 14 cm -3和1×10 15 cm -3的范围内的掺杂浓度和 第二深度（55），其最大为50μm。 通过使用铝扩散层作为至少两个子层（51,52,53）来实现掺杂浓度的这种分布。