公开(公告)号：WO1997035251A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001065

申请日：1997-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf ,  IRETON, Mark ,  BARTKOWIAK, John, G.

IPC: G06F09/38

CPC classification number: G06F9/3017 ,  G06F9/3879 ,  G06F9/3885 ,  H04Q2213/13036 ,  H04Q2213/1305 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13199 ,  H04Q2213/13299 ,  H04Q2213/13389 ,  H04Q2213/13396

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Abstract translation: 包括通用CPU组件（如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括一个智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。 如果指令高速缓存或指令存储器中的X86操作码不表示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。 因此，DSP核心从X86内核卸载这些数学函数，从而提高系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：WO1997035249A1

公开(公告)日：1997-09-25

申请号：PCT/US1996019585

申请日：1996-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf ,  IRETON, Mark, A. ,  BARTKOWIAK, John, G.

IPC: G06F09/38

CPC classification number: G06F9/3017 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7857

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Abstract translation: 包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。 如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。 因此，DSP核心从X86内核中卸载了这些数学函数，从而提高了系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：WO1997035252A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001067

申请日：1997-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf ,  IRETON, Mark ,  BARTKOWIAK, John

IPC: G06F09/38

CPC classification number: G06F9/3822 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7857

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Abstract translation: 包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。 如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。 因此，DSP核心从X86内核中卸载了这些数学函数，从而提高了系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：WO1997035250A1

公开(公告)日：1997-09-25

申请号：PCT/US1996019586

申请日：1996-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf ,  IRETON, Mark, A. ,  BARTKOWIAK, John, G.

IPC: G06F09/38

CPC classification number: G06F9/382 ,  G06F9/3017 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7857

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Abstract translation: 包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。 如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。 因此，DSP核心从X86内核中卸载了这些数学函数，从而提高了系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：WO1997035244A2

公开(公告)日：1997-09-25

申请号：PCT/US1996019584

申请日：1996-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf ,  IRETON, Mark, A. ,  BARTKOWIAK, John, G.

IPC: G06F00/00

CPC classification number: G06F9/3017 ,  G06F9/3822 ,  G06F9/3879

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Abstract translation: 包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。 如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。 因此，DSP核心从X86内核中卸载了这些数学函数，从而提高了系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：EP1036358A1

公开(公告)日：2000-09-20

申请号：EP98923500.7

申请日：1998-05-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ASGHAR, Saf ,  MILLS, Andrew

IPC: G06F9/318 ,  G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F15/7857

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instru tions to implement the desired DSP function in response to the mcro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.

公开(公告)号：EP0888584B1

公开(公告)日：2003-09-10

申请号：EP97903929.4

申请日：1997-01-23

Applicant: Advanced Micro Devices, Inc.

Inventor： ASGHAR, Saf ,  IRETON, Mark ,  BARTKOWIAK, John

IPC: G06F9/38 ,  G06F9/318 ,  G06F15/78

CPC classification number: G06F9/3822 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7857

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

公开(公告)号：EP0888584A1

公开(公告)日：1999-01-07

申请号：EP97903929.0

申请日：1997-01-23

Applicant: Advanced Micro Devices, Inc.

Inventor： ASGHAR, Saf ,  IRETON, Mark ,  BARTKOWIAK, John

IPC: G06F9 ,  G06F15

CPC classification number: G06F9/3822 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7857

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.