公开(公告)号：WO2004040655A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/035437

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

Abstract: An insulated gate field effect semiconductor component (100) having a source-side halo region (120) and a method for manufacturing the semiconductor component (100). A gate structure (112) is formed on a semiconductor substrate (102). The source-side halo region (120) is formed in the semiconductor substrate (102). After formation of the source-side halo region (120), spacers (127, 128, 152, 154) are formed adjacent opposing sides of the gate structure (112). A source extension region (136A) and a drain extension region (138A) are formed in the semiconductor substrate (102) using an angled implant. The source extension region (136A) extends under the gate structure (112), whereas the drain extension region (138A) may extend under the gate structure (112) or be laterally spaced apart from the gate structure (112). A source region (156) and a drain region (158) are formed in the semiconductor substrate (102).

Abstract translation: 具有源极侧晕区（120）的绝缘栅场效应半导体组件（100）以及用于制造半导体组件（100）的方法。 栅极结构（112）形成在半导体衬底（102）上。 源极侧晕区（120）形成在半导体衬底（102）中。 在形成源极侧晕环区域（120）之后，在栅极结构（112）的相对侧面附近形成间隔物（127,128,152,154）。 使用倾斜注入在半导体衬底（102）中形成源极延伸区域（136A）和漏极延伸区域（138A）。 源极延伸区域（136A）在栅极结构（112）下方延伸，而漏极延伸区域（138A）可在栅极结构（112）下方延伸或与栅极结构（112）横向间隔开。 源区（156）和漏区（158）形成在半导体衬底（102）中。

公开(公告)号：WO2006049833A1

公开(公告)日：2006-05-11

申请号：PCT/US2005/036777

申请日：2005-10-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  WAITE, Andrew, M. ,  CHEEK, Jon

Inventor： WAITE, Andrew, M. ,  CHEEK, Jon

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78654

Abstract: A semiconductor device comprising a substrate 12 having a first crystal orientation and an insulating layer 40 overlying the substrate 12 is provided. A plurality of silicon layers 16, 30 are formed overlying the insulating layer 40. A first silicon layer 16 comprises silicon having the first crystal orientation and a second silicon layer 30 comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate 12 with a silicon layer 16 overlying the substrate 12 and a first insulating layer 14 interposed therebetween is provided. An opening 22 is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer 16 and the first insulating layer 14 to expose a portion 24 of the substrate layer 12. Selective epitaxial silicon 30 is grown in the opening. A second insulating layer 40 is formed in the silicon 30 grown in the opening 22 to provide an insulating layer 40 between the grown silicon 30 in the opening 22 and the substrate 12.

Abstract translation: 提供了包括具有第一晶体取向的基板12和覆盖在基板12上的绝缘层40的半导体器件。 多个硅层16,30形成在绝缘层40上。第一硅层16包括具有第一晶体取向的硅，而第二硅层30包含具有第二晶体取向的硅。 此外，提供了一种形成提供绝缘体上硅结构的半导体器件的方法，其包括具有覆盖在衬底12上的硅层16的衬底12和插入其间的第一绝缘层14。 通过去除硅层16和第一绝缘层14的一部分以露出衬底层12的部分24，在绝缘体上硅结构的第一区域中形成开口22.选择性外延硅30生长在 开幕。 在开口22中生长的硅30中形成第二绝缘层40，以在开口22中生长的硅30和基板12之间提供绝缘层40。

公开(公告)号：WO2004040637A1

公开(公告)日：2004-05-13

申请号：PCT/US2003/035436

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated gate field effect transistor (10) having differentially doped source-side (36A) and drain-side (42A) halo regions and a method for manufacturing the transistor (10). A source-side halo region (36A) is proximal a source extension region (48) and a drain-side halo region (42A) is proximal a drain extension region (52), where the drain-side halo region (42A) has a higher dopant concentration than the source-side halo region (36A). The source extension region (48) extends under a gate structure (22), whereas the drain extension region (52) may extend under the gate structure (22) or be laterally spaced apart from the gate structure (22) or be aligned to the side (26) of the gate structure (22) adjacent the drain region (54). A source region (53) is adjacent the source extension region (48) and a drain region (54) is adjacent the drain extension region (52).

Abstract translation: 具有差分掺杂源极侧（36A）和漏极侧（42A）晕区的绝缘栅场效应晶体管（10）和制造晶体管（10）的方法。 源侧晕区（36A）在源极延伸区（48）附近，漏极侧晕区（42A）靠近漏极延伸区（52），其中漏极侧晕区（42A）具有 比源侧卤素区域（36A）更高的掺杂剂浓度。 源极延伸区域（48）在栅极结构（22）的下方延伸，而漏极延伸区域（52）可以在栅极结构（22）的下方延伸或者与栅极结构（22）横向间隔开或者与 邻近漏区（54）的栅结构（22）的侧（26）。 源极区域（53）与源极延伸区域（48）相邻，漏极区域（54）与漏极延伸区域（52）相邻。

公开(公告)号：EP1815520B1

公开(公告)日：2012-05-02

申请号：EP05812444.7

申请日：2005-10-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WAITE, Andrew, M. ,  CHEEK, Jon

IPC: H01L21/336 ,  H01L29/04 ,  H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78654

Abstract: A semiconductor device comprising a substrate 12 having a first crystal orientation and an insulating layer 40 overlying the substrate 12 is provided. A plurality of silicon layers 16, 30 are formed overlying the insulating layer 40. A first silicon layer 16 comprises silicon having the first crystal orientation and a second silicon layer 30 comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate 12 with a silicon layer 16 overlying the substrate 12 and a first insulating layer 14 interposed therebetween is provided. An opening 22 is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer 16 and the first insulating layer 14 to expose a portion 24 of the substrate layer 12. Selective epitaxial silicon 30 is grown in the opening. A second insulating layer 40 is formed in the silicon 30 grown in the opening 22 to provide an insulating layer 40 between the grown silicon 30 in the opening 22 and the substrate 12.

公开(公告)号：EP1559144A2

公开(公告)日：2005-08-03

申请号：EP03768744.9

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

Abstract: An insulated gate field effect semiconductor component (100) having a source-side halo region (120) and a method for manufacturing the semiconductor component (100). A gate structure (112) is formed on a semiconductor substrate (102). The source-side halo region (120) is formed in the semiconductor substrate (102). After formation of the source-side halo region (120), spacers (127, 128, 152, 154) are formed adjacent opposing sides of the gate structure (112). A source extension region (136A) and a drain extension region (138A) are formed in the semiconductor substrate (102) using an angled implant. The source extension region (136A) extends under the gate structure (112), whereas the drain extension region (138A) may extend under the gate structure (112) or be laterally spaced apart from the gate structure (112). A source region (156) and a drain region (158) are formed in the semiconductor substrate (102).

公开(公告)号：EP1815520A1

公开(公告)日：2007-08-08

申请号：EP05812444.7

申请日：2005-10-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WAITE, Andrew, M. ,  CHEEK, Jon

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78654

Abstract: A semiconductor device comprising a substrate 12 having a first crystal orientation and an insulating layer 40 overlying the substrate 12 is provided. A plurality of silicon layers 16, 30 are formed overlying the insulating layer 40. A first silicon layer 16 comprises silicon having the first crystal orientation and a second silicon layer 30 comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate 12 with a silicon layer 16 overlying the substrate 12 and a first insulating layer 14 interposed therebetween is provided. An opening 22 is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer 16 and the first insulating layer 14 to expose a portion 24 of the substrate layer 12. Selective epitaxial silicon 30 is grown in the opening. A second insulating layer 40 is formed in the silicon 30 grown in the opening 22 to provide an insulating layer 40 between the grown silicon 30 in the opening 22 and the substrate 12.