公开(公告)号：WO2004040637A1

公开(公告)日：2004-05-13

申请号：PCT/US2003/035436

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated gate field effect transistor (10) having differentially doped source-side (36A) and drain-side (42A) halo regions and a method for manufacturing the transistor (10). A source-side halo region (36A) is proximal a source extension region (48) and a drain-side halo region (42A) is proximal a drain extension region (52), where the drain-side halo region (42A) has a higher dopant concentration than the source-side halo region (36A). The source extension region (48) extends under a gate structure (22), whereas the drain extension region (52) may extend under the gate structure (22) or be laterally spaced apart from the gate structure (22) or be aligned to the side (26) of the gate structure (22) adjacent the drain region (54). A source region (53) is adjacent the source extension region (48) and a drain region (54) is adjacent the drain extension region (52).

Abstract translation: 具有差分掺杂源极侧（36A）和漏极侧（42A）晕区的绝缘栅场效应晶体管（10）和制造晶体管（10）的方法。 源侧晕区（36A）在源极延伸区（48）附近，漏极侧晕区（42A）靠近漏极延伸区（52），其中漏极侧晕区（42A）具有 比源侧卤素区域（36A）更高的掺杂剂浓度。 源极延伸区域（48）在栅极结构（22）的下方延伸，而漏极延伸区域（52）可以在栅极结构（22）的下方延伸或者与栅极结构（22）横向间隔开或者与 邻近漏区（54）的栅结构（22）的侧（26）。 源极区域（53）与源极延伸区域（48）相邻，漏极区域（54）与漏极延伸区域（52）相邻。

公开(公告)号：WO2004040655A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/035437

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

Abstract: An insulated gate field effect semiconductor component (100) having a source-side halo region (120) and a method for manufacturing the semiconductor component (100). A gate structure (112) is formed on a semiconductor substrate (102). The source-side halo region (120) is formed in the semiconductor substrate (102). After formation of the source-side halo region (120), spacers (127, 128, 152, 154) are formed adjacent opposing sides of the gate structure (112). A source extension region (136A) and a drain extension region (138A) are formed in the semiconductor substrate (102) using an angled implant. The source extension region (136A) extends under the gate structure (112), whereas the drain extension region (138A) may extend under the gate structure (112) or be laterally spaced apart from the gate structure (112). A source region (156) and a drain region (158) are formed in the semiconductor substrate (102).

Abstract translation: 具有源极侧晕区（120）的绝缘栅场效应半导体组件（100）以及用于制造半导体组件（100）的方法。 栅极结构（112）形成在半导体衬底（102）上。 源极侧晕区（120）形成在半导体衬底（102）中。 在形成源极侧晕环区域（120）之后，在栅极结构（112）的相对侧面附近形成间隔物（127,128,152,154）。 使用倾斜注入在半导体衬底（102）中形成源极延伸区域（136A）和漏极延伸区域（138A）。 源极延伸区域（136A）在栅极结构（112）下方延伸，而漏极延伸区域（138A）可在栅极结构（112）下方延伸或与栅极结构（112）横向间隔开。 源区（156）和漏区（158）形成在半导体衬底（102）中。

公开(公告)号：WO2005017993A1

公开(公告)日：2005-02-24

申请号：PCT/US2004/017708

申请日：2004-06-04

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUSELIER, Mark, B. ,  EHRICHS, Edward, E. ,  RAY, S., Doug ,  WEINTRAUB, Chad ,  BULLER, James, F.

Inventor： FUSELIER, Mark, B. ,  EHRICHS, Edward, E. ,  RAY, S., Doug ,  WEINTRAUB, Chad ,  BULLER, James, F.

IPC: H01L21/336

CPC classification number: H01L21/823468 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/66742 ,  H01L29/6678 ,  H01L29/78654 ,  H01L29/78657

Abstract: A method for asymmetric spacer formation integratable into a manufacturing process for integrated circuit semiconductor devices is presented. The method comprises forming a gate structure (15) over a substrate, and forming a sidewall layer (10) overlying the gate structure and substrate, wherein the sidewall layer comprises a first portion overlying a first sidewall of the gate structure. A photoresist structure (11) is formed adjacent to the first portion, and subjected to an ion beam. The photoresist structure serves to shield at least part of the first portion from the ion beam. During irradiation, the wafer is oriented such that a non-orthogonal tilt angle exists between a path of the ion beam (13, 17) and a surface of the first sidewall. Formation of asymmetric spacers is possible because radiation damage to unshielded sidewall portions permits subsequent etches to proceed at a faster rate.

Abstract translation: 提出了可集成到集成电路半导体器件的制造工艺中的非对称间隔物形成方法。 该方法包括在衬底上形成栅极结构（15），并且形成覆盖栅极结构和衬底的侧壁层（10），其中侧壁层包括覆盖栅极结构的第一侧壁的第一部分。 光致抗蚀剂结构（11）与第一部分相邻地形成，并进行离子束。 光致抗蚀剂结构用于将第一部分的至少一部分与离子束屏蔽。 在照射期间，晶片被定向成使得在离子束（13,17）的路径和第一侧壁的表面之间存在非正交倾斜角。 不对称间隔物的形成是可能的，因为对非屏蔽侧壁部分的辐射损伤允许随后的蚀刻以更快的速率进行。

公开(公告)号：EP1559144A2

公开(公告)日：2005-08-03

申请号：EP03768744.9

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

Abstract: An insulated gate field effect semiconductor component (100) having a source-side halo region (120) and a method for manufacturing the semiconductor component (100). A gate structure (112) is formed on a semiconductor substrate (102). The source-side halo region (120) is formed in the semiconductor substrate (102). After formation of the source-side halo region (120), spacers (127, 128, 152, 154) are formed adjacent opposing sides of the gate structure (112). A source extension region (136A) and a drain extension region (138A) are formed in the semiconductor substrate (102) using an angled implant. The source extension region (136A) extends under the gate structure (112), whereas the drain extension region (138A) may extend under the gate structure (112) or be laterally spaced apart from the gate structure (112). A source region (156) and a drain region (158) are formed in the semiconductor substrate (102).