公开(公告)号：WO1998010464A1

公开(公告)日：1998-03-12

申请号：PCT/US1997004986

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAO, Ming-Yin ,  OGLE, Robert, B., Jr. ,  WRISTERS, Derick

IPC: H01L21/28

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract translation: 描述了用于生长用作MOSFET栅极氧化物或用于EEPROM的隧道氧化物的超薄介电层的工艺。 通过一氧化氮和一氧化二氮气体中的一系列退火形成氮氧化物层，其在晶圆 - 氧氮化物界面处和氧氮化物表面处的氮浓度具有峰值，并且在氮氧化物本体中具有低氮浓度。 该方法提供精确的厚度控制，改进的界面结构，电子陷阱的低密度，并阻止从介质和衬底扩散掺杂剂杂质。 该过程很容易集成到现有的制造过程中，并且增加了很少的成本。

公开(公告)号：WO2004040637A1

公开(公告)日：2004-05-13

申请号：PCT/US2003/035436

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated gate field effect transistor (10) having differentially doped source-side (36A) and drain-side (42A) halo regions and a method for manufacturing the transistor (10). A source-side halo region (36A) is proximal a source extension region (48) and a drain-side halo region (42A) is proximal a drain extension region (52), where the drain-side halo region (42A) has a higher dopant concentration than the source-side halo region (36A). The source extension region (48) extends under a gate structure (22), whereas the drain extension region (52) may extend under the gate structure (22) or be laterally spaced apart from the gate structure (22) or be aligned to the side (26) of the gate structure (22) adjacent the drain region (54). A source region (53) is adjacent the source extension region (48) and a drain region (54) is adjacent the drain extension region (52).

Abstract translation: 具有差分掺杂源极侧（36A）和漏极侧（42A）晕区的绝缘栅场效应晶体管（10）和制造晶体管（10）的方法。 源侧晕区（36A）在源极延伸区（48）附近，漏极侧晕区（42A）靠近漏极延伸区（52），其中漏极侧晕区（42A）具有 比源侧卤素区域（36A）更高的掺杂剂浓度。 源极延伸区域（48）在栅极结构（22）的下方延伸，而漏极延伸区域（52）可以在栅极结构（22）的下方延伸或者与栅极结构（22）横向间隔开或者与 邻近漏区（54）的栅结构（22）的侧（26）。 源极区域（53）与源极延伸区域（48）相邻，漏极区域（54）与漏极延伸区域（52）相邻。

公开(公告)号：WO2004040655A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/035437

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

Abstract: An insulated gate field effect semiconductor component (100) having a source-side halo region (120) and a method for manufacturing the semiconductor component (100). A gate structure (112) is formed on a semiconductor substrate (102). The source-side halo region (120) is formed in the semiconductor substrate (102). After formation of the source-side halo region (120), spacers (127, 128, 152, 154) are formed adjacent opposing sides of the gate structure (112). A source extension region (136A) and a drain extension region (138A) are formed in the semiconductor substrate (102) using an angled implant. The source extension region (136A) extends under the gate structure (112), whereas the drain extension region (138A) may extend under the gate structure (112) or be laterally spaced apart from the gate structure (112). A source region (156) and a drain region (158) are formed in the semiconductor substrate (102).

Abstract translation: 具有源极侧晕区（120）的绝缘栅场效应半导体组件（100）以及用于制造半导体组件（100）的方法。 栅极结构（112）形成在半导体衬底（102）上。 源极侧晕区（120）形成在半导体衬底（102）中。 在形成源极侧晕环区域（120）之后，在栅极结构（112）的相对侧面附近形成间隔物（127,128,152,154）。 使用倾斜注入在半导体衬底（102）中形成源极延伸区域（136A）和漏极延伸区域（138A）。 源极延伸区域（136A）在栅极结构（112）下方延伸，而漏极延伸区域（138A）可在栅极结构（112）下方延伸或与栅极结构（112）横向间隔开。 源区（156）和漏区（158）形成在半导体衬底（102）中。

公开(公告)号：WO1997037380A1

公开(公告)日：1997-10-09

申请号：PCT/US1997003885

申请日：1997-03-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FULFORD, H., Jim, Jr. ,  WRISTERS, Derick

IPC: H01L21/66

CPC classification number: H01L22/20 ,  Y10S148/003 ,  Y10S148/122 ,  Y10S148/137

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.

Abstract translation: 晶体管驱动电流是通过基于集成电路参数可控地改变半导体衬底晶片上的曝光来控制的。 曝光变化的集成电路参数包括栅极氧化物厚度，快速温度退火（RTA）温度，多晶偏压等。

公开(公告)号：EP0928497A1

公开(公告)日：1999-07-14

申请号：EP97917648.0

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HAO, Ming-Yin ,  OGLE, Robert, B., Jr. ,  WRISTERS, Derick

IPC: H01L21 ,  H01L27 ,  H01L29

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

公开(公告)号：EP1559144A2

公开(公告)日：2005-08-03

申请号：EP03768744.9

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WRISTERS, Derick ,  WEINTRAUB, Chad ,  BULLER, James, F. ,  CHEEK, Jon

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

Abstract: An insulated gate field effect semiconductor component (100) having a source-side halo region (120) and a method for manufacturing the semiconductor component (100). A gate structure (112) is formed on a semiconductor substrate (102). The source-side halo region (120) is formed in the semiconductor substrate (102). After formation of the source-side halo region (120), spacers (127, 128, 152, 154) are formed adjacent opposing sides of the gate structure (112). A source extension region (136A) and a drain extension region (138A) are formed in the semiconductor substrate (102) using an angled implant. The source extension region (136A) extends under the gate structure (112), whereas the drain extension region (138A) may extend under the gate structure (112) or be laterally spaced apart from the gate structure (112). A source region (156) and a drain region (158) are formed in the semiconductor substrate (102).

公开(公告)号：EP0890188A1

公开(公告)日：1999-01-13

申请号：EP97909017.0

申请日：1997-03-12

Applicant: Advanced Micro Devices, Inc.

Inventor： FULFORD, H., Jim, Jr. ,  WRISTERS, Derick

IPC: H01L21 ,  G03F7

CPC classification number: H01L22/20 ,  Y10S148/003 ,  Y10S148/122 ,  Y10S148/137

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.