公开(公告)号：WO1997016830A1

公开(公告)日：1997-05-09

申请号：PCT/US1996012020

申请日：1996-07-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee, E. ,  CHEN, Johnny, C.

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/28 ,  G11C16/3404

Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.

Abstract translation: 用于闪速存储器中过度修正的参考电路包括以基本上类似于过度闪存单元的方式偏置的参考闪存单元。 参考闪存单元的泄漏电流被预设为在闪速存储器的最大工作温度下允许的泄漏电流水平，并且参考闪速存储器单元跟踪过高闪存单元的温度特性，以避免在高处过高的过高校正 温度。

公开(公告)号：WO1998039773A1

公开(公告)日：1998-09-11

申请号：PCT/US1997014454

申请日：1997-08-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHEN, Johnny, C. ,  CHANG, Chung, K.

IPC: G11C08/00

CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals ot store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.

Abstract translation: 一种非易失性存储器，允许通过在读取和写入操作之间对单个x-decode路径进行时间复用来同时进行读写操作。 这是使用适当的定时信号完成的，该定时信号不存储/锁存用于第一操作的第一字线，然后放弃x解码路径，使得第二操作可以加载地址并访问第二字线。

公开(公告)号：WO1998028750A1

公开(公告)日：1998-07-02

申请号：PCT/US1997020819

申请日：1997-11-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED ,  CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C2216/22

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

Abstract translation: 闪存器件分为两个或更多个存储体。 每个银行都包括一些行业。 每个扇区包括闪存单元。 每个存储体都有一个解码器，可选择性地从输入地址缓冲区或内部地址定序器接收由内部状态机控制的地址。 每个存储体的输出数据可以传送到读出读出放大器或验证读出放大器。 读出放大器连接到输出缓冲器，而验证放大器连接到状态机。 当一个银行收到一个写命令时，内部状态机接受控制并启动程序或擦除操作。 当一个银行忙于编程或擦除操作时，可以访问另一个存储体进行读取操作。

公开(公告)号：WO1997030455A1

公开(公告)日：1997-08-21

申请号：PCT/US1996013232

申请日：1996-08-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC: G11C16/06

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract translation: 用于在闪速擦除期间通过闪存EEPROM存储器单元阵列中的字线产生相对高的负电压以控制所选择的存储器单元的栅极的低电源负电荷泵包括由多个电荷泵级形成的电荷泵装置（210） 201-206）和用于将时钟信号传送到多个电荷泵级的耦合电容器装置（C201-C212）。 多个电荷泵级中的每一个由N沟道本征通过晶体管（N1-N6），N沟道本征初始化晶体管（MD1-MD6）和N沟道本征预充电晶体管（MX3-MX7， MX1），其设置在单独的p阱中，以减少身体效应。 结果，负电荷泵可以使用+ 3伏或更低的电源电压工作。

公开(公告)号：EP0944907B1

公开(公告)日：2001-10-17

申请号：EP97947516.7

申请日：1997-11-13

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C2216/22

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

公开(公告)号：EP0880783B1

公开(公告)日：1999-10-13

申请号：EP96927429.9

申请日：1996-08-15

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC: G11C16/06 ,  G11C5/14 ,  H02M3/07

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

公开(公告)号：EP0944907A1

公开(公告)日：1999-09-29

申请号：EP97947516.0

申请日：1997-11-13

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

IPC: G11C16

CPC classification number: G11C16/10 ,  G11C2216/22

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

公开(公告)号：EP0880783A1

公开(公告)日：1998-12-02

申请号：EP96927429.0

申请日：1996-08-15

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC: G11C5 ,  G11C16 ,  H02M3

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

公开(公告)号：EP0965130B1

公开(公告)日：2001-10-24

申请号：EP97937295.0

申请日：1997-08-15

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHEN, Johnny, C. ,  CHANG, Chung, K.

IPC: G11C8/00 ,  G11C16/06

CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals ot store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.

公开(公告)号：EP0965130A1

公开(公告)日：1999-12-22

申请号：EP97937295.0

申请日：1997-08-15

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHEN, Johnny, C. ,  CHANG, Chung, K.

IPC: G11C16 ,  G11C8

CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals ot store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.