公开(公告)号：WO1997044740A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008363

申请日：1997-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LAMBRECHT, Andy ,  SWANSTROM, Scott ,  DUTTON, Drew

IPC: G06F13/40

CPC classification number: G06F13/36 ,  G06F13/124 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4022 ,  G06F13/4027 ,  H04N21/238

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract translation: 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，如PCI总线，还包括一个专用的实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的专用或集中的I / O处理器，其操作以通过系统引导或引导流信息。 集中式I / O处理器包括用于存储用于所述多媒体设备的数据速率，数据周期，数据源和数据目的地信息的存储器。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：WO1997023828A1

公开(公告)日：1997-07-03

申请号：PCT/US1996012005

申请日：1996-07-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MACDONALD, James, R. ,  DUTTON, Drew ,  COX, Steve

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/401

Abstract: A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompressing pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

Abstract translation: 用于具有存储器和执行单元的计算机的存储器寻呼和压缩系统包括地址映射层级，压缩页面映射层级，翻译后端缓冲器和压缩/解压缩组件。 地址映射层次结构包括具有从虚拟地址的第一部分映射到物理存储器中的相应页面的页表条目的页表。 压缩页面映射层级包括具有从虚拟地址的第一部分映射到物理存储器中的相应压缩页面的压缩页表项的压缩页表。 翻译后备缓冲区最近缓存了从虚拟地址的第一部分到物理存储器中各页的映射关系。 压缩/解压缩组件包括耦合在存储器和执行单元之间的压缩/解压缩引擎，用于交替地压缩和解压缩存储器中的页面，以分别对应于来自翻译后备缓冲器的溢出和加载。 地址映射层级和压缩页映射层次可以在存储器中表示，并且压缩/解压缩组件还可以包括解压缩故障处理程序和压缩故障处理程序，每个执行单元都可执行。

公开(公告)号：EP0976045A1

公开(公告)日：2000-02-02

申请号：EP96924645.3

申请日：1996-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： MACDONALD, James, R. ,  DUTTON, Drew ,  COX, Steve

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/023 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/401

Abstract: A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompressing pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

公开(公告)号：EP0898749B1

公开(公告)日：2001-09-26

申请号：EP97926565.9

申请日：1997-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： LAMBRECHT, Andy ,  SWANSTROM, Scott ,  DUTTON, Drew

IPC: G06F13/40 ,  G06F13/12

CPC classification number: G06F13/36 ,  G06F13/124 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4022 ,  G06F13/4027 ,  H04N21/238

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

公开(公告)号：EP0976045B1

公开(公告)日：2002-04-24

申请号：EP96924645.3

申请日：1996-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： MACDONALD, James, R. ,  DUTTON, Drew ,  COX, Steve

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/023 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/401

Abstract: A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompressing pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

公开(公告)号：EP0898749A1

公开(公告)日：1999-03-03

申请号：EP97926565.0

申请日：1997-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： LAMBRECHT, Andy ,  SWANSTROM, Scott ,  DUTTON, Drew

IPC: G06F13 ,  H04N7

CPC classification number: G06F13/36 ,  G06F13/124 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4022 ,  G06F13/4027 ,  H04N21/238

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.