公开(公告)号：WO1998023069A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021467

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Abstract translation: 一种使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差的相位检测器。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈回路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较，以产生两个数字信号：接收信号的同相（I）和正交相位（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减少I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差并构造与该差成比例的相位误差信号来确定相位误差信号的大小。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。

公开(公告)号：WO1997024652A1

公开(公告)日：1997-07-10

申请号：PCT/US1996016463

申请日：1996-10-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHELDON, Peter ,  SCHNIZLEIN, Paul ,  HENDRICKSON, Alan

IPC: G06F01/24

CPC classification number: G06F1/28 ,  G06F1/24 ,  G06F1/30 ,  G06F11/0757 ,  H03K17/22

Abstract: A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

Abstract translation: 公开了一种在集成电路中并入电池监视器和看门狗定时器的复位电路。 具有指示电池的充电状态的输出的电池监视器和具有指示由集成电路执行的软件的操作状态的输出的看门狗定时器被连接到具有复位信号输出的复位逻辑，其中复位逻辑产生 如果电池监视器输出或看门狗定时器输出有效，则复位信号输出上的复位信号。

公开(公告)号：WO1997036245A1

公开(公告)日：1997-10-02

申请号：PCT/US1997005025

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HENDRICKSON, Alan

IPC: G06F13/42

CPC classification number: G06F13/423

Abstract: A serial communication system including a serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By emitting a clock output pulse train of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device. The location of data boundaries relative to the clock phase is programmable such that the data boundaries coincide with active clock edges.

Abstract translation: 一种串行通信系统，包括用于启动和停止内部时钟的串行通信端口结构。 该内部时钟在工作时被设计为产生时钟输出信号，以将其发送到并入串行通信端口的系统外部的设备。 通过发出预定长度的时钟输出脉冲串，串行通信端口可以有效地控制外部设备感测到的时间的流逝。 相对于时钟相位的数据边界的位置是可编程的，使得数据边界与活动时钟边沿重合。

公开(公告)号：WO1997030540A1

公开(公告)日：1997-08-21

申请号：PCT/US1997001797

申请日：1997-02-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MULLINS, Jacqueline ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04M01/72

CPC classification number: H04M1/733 ,  H04M1/72502

Abstract: An apparatus for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The apparatus comprises a radio interface connection with the frame formatter, for delivering and receiving the transmitted baseband signal and the received baseband signal, respectively, a FIFO/codec interface connected with the frame formatter, an interrupt interface connected with the frame formatter, a control register interface connected with the frame formatter, and a microcontroller interface connected with the frame formatter.

Abstract translation: 一种用于数字无绳电信的装置包括用于逻辑信道格式化发送的基带信号和接收的基带信号的帧格式化器。 该装置包括与帧格式化器的无线电接口连接，用于分别传送和接收所发送的基带信号和接收的基带信号，与帧格式器连接的FIFO /编解码器接口，与帧格式化器连接的中断接口，控制 与帧格式器连接的寄存器接口，以及与帧格式器连接的微控制器接口。

公开(公告)号：WO1998023070A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021468

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A digital communications DQPSK passband detector having a matched filter, a differential decoder, and a slicer that use elementary circuit components. In the matched filter, recovered carrier references signals are fed along with the received signal to a pair of XNOR gates. This arrangement effectively results in a multiplication operation without any complex circuit elements. The outputs of the XNOR gates control the direction of counting of a pair of binary counters that generate correlated values of the I and Q components in the received signal. Thus, the integrate/dump circuits of a conventional matched filter are replaced with simpler digital counters. A digital differential decoder to extract the phase difference information between two consecutive received symbols is built from a network of delay elements, multipliers, and adders to recover the phase data. The digital differential decoder produces a digital complex-signal output that can be quantized in a digital slicer to decode the plurality of binary bits transmitted through the data symbols. All these operations are performed on digital signals with basic digital circuit elements, thus resulting in a repeatable robust receiver design without complex hardware components.

Abstract translation: 具有匹配滤波器的数字通信DQPSK通带检测器，差分解码器和使用基本电路部件的限幅器。 在匹配滤波器中，恢复的载波参考信号与接收信号一起馈送到一对XNOR门。 这种布置有效地导致没有任何复杂电路元件的乘法运算。 XNOR门的输出控制一对二进制计数器的计数方向，产生接收信号中I和Q分量的相关值。 因此，常规匹配滤波器的集成/转储电路被更简单的数字计数器代替。 从延迟元件，乘法器和加法器的网络构建用于提取两个连续的接收符号之间的相位差信息的数字差分解码器，以恢复相位数据。 数字差分解码器产生可在数字限幅器中量化的数字复信号输出，以对通过数据符号传输的多个二进制位进行解码。 所有这些操作都是用具有基本数字电路元件的数字信号执行的，从而导致可重复的鲁棒接收机设计，而无需复杂的硬件组件。

公开(公告)号：WO1998023042A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021369

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HENDRICKSON, Alan

IPC: H04B01/707

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A system for recognizing degraded pseudo-random noise (PN) synchronization in a spread-spectrum receiver. The system uses a signal that indicates the correlation of the locally generated PN sequence with the received PN sequence. The correlation signal can be a symbol-length integration of the output from a square-law detector, or an appropriate similar signal. If the correlation signal is not degraded by demodulating with a deliberately shifted copy of the PN sequence, there is an indication that the unshifted PN sequence was itself not correctly synchronized. A sufficiently degraded correlation signal indicates that the receiver's PN synchronization is correct. To prevent the loss of transmitted data during the testing, each transmitted frame contains a Measurement field (that contains no payload data) for assessing the synchronization in this manner. The PN sequence is shifted only during this specific portion of the received frame.

Abstract translation: 一种用于识别扩频接收机中的劣化伪随机噪声（PN）同步的系统。 该系统使用指示本地生成的PN序列与接收的PN序列的相关性的信号。 相关信号可以是来自平方律检测器的输出或适当的相似信号的符号长度积分。 如果通过用PN序列的故意移位副本进行解调来降低相关信号，则存在未被移位的PN序列本身未正确同步的指示。 充分劣化的相关信号表示接收机的PN同步是正确的。 为了防止在测试期间发送的数据的丢失，每个发送的帧包含用于以这种方式评估同步的测量字段（不包含有效载荷数据）。 PN序列仅在接收帧的特定部分移动。

公开(公告)号：EP0882258A1

公开(公告)日：1998-12-09

申请号：EP96936490.0

申请日：1996-10-15

Applicant: Advanced Micro Devices, Inc.

Inventor： SHELDON, Peter ,  SCHNIZLEIN, Paul ,  HENDRICKSON, Alan

IPC: G06F1 ,  H03K17 ,  G06F11

CPC classification number: G06F1/28 ,  G06F1/24 ,  G06F1/30 ,  G06F11/0757 ,  H03K17/22

Abstract: A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

公开(公告)号：EP0882258B1

公开(公告)日：2000-07-26

申请号：EP96936490.0

申请日：1996-10-15

Applicant: Advanced Micro Devices, Inc. ,  VTech Communications, Ltd.

Inventor： SHELDON, Peter ,  SCHNIZLEIN, Paul ,  HENDRICKSON, Alan

IPC: G06F1/24

CPC classification number: G06F1/28 ,  G06F1/24 ,  G06F1/30 ,  G06F11/0757 ,  H03K17/22

Abstract: A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.