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    TRANSMIT CLOCK GENERATION SYSTEM AND METHOD
    1.
    发明申请
    TRANSMIT CLOCK GENERATION SYSTEM AND METHOD 审中-公开
    发送时钟生成系统和方法

    公开(公告)号：WO1997036375A1

    公开(公告)日：1997-10-02

    申请号：PCT/US1997004875

    申请日：1997-03-25

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  SCHNIZLEIN, Paul

    IPC: H03L07/099

    CPC classification number: H03L7/0805 ,  H03L7/089 ,  H03L7/0992 ,  H04L7/0331

    Abstract: The communications system includes a first communications unit (2) and a second communications unit, each capable of communication with the other. The first communications unit has a first internal clock and the second communications unit has a second internal clock. The method includes the steps of receiving a receive signal (4) by the first communications unit (2) from the second communications unit, adjusting the receive signal (4) to obtain an adjusted receive clock signal (60) that tracks the receive data signal (4), accumulating the adjustments made in the adjusting step, applying the adjustments accumulated to vary the first internal clock in order to slave the first internal clock to the second internal clock of the second communications unit so as to obtain an adjusted signal (34) that is the adjusted and slaved first internal clock, and deriving a transmit clock (62) from the adjusted signal. With this method, the transmit clock (62) exhibits substantially less jitter because it is not directly derived from the jittered receive clock signal (60). The invention may in particular be applied to communication between a base set unit and handset unit of a digital cordless telephone.

    Abstract translation: 通信系统包括第一通信单元（2）和第二通信单元，每个通信单元能够彼此通信。 第一通信单元具有第一内部时钟，第二通信单元具有第二内部时钟。 该方法包括以下步骤：从第二通信单元接收第一通信单元（2）的接收信号（4），调整接收信号（4）以获得调整的接收时钟信号（60），其跟踪接收数据信号 （4），累积在调整步骤中进行的调整，施加累积的调整以改变第一内部时钟，以便将第一内部时钟从第二通信单元的第二内部时钟引起，从而获得调整后的信号（34 ），其是经调整和从动的第一内部时钟，并且根据经调整的信号导出发送时钟（62）。 利用这种方法，由于传输时钟（62）不直接从抖动的接收时钟信号（60）导出，所以传输时钟（62）显示出较小的抖动。 本发明可以特别地应用于数字无绳电话的基站单元和手机单元之间的通信。

    PASSBAND DQPSK DETECTOR FOR A DIGITAL COMMUNICATIONS RECEIVER
    2.
    发明申请
    PASSBAND DQPSK DETECTOR FOR A DIGITAL COMMUNICATIONS RECEIVER 审中-公开
    用于数字通信接收机的PASSBAND DQPSK检测器

    公开(公告)号：WO1998023070A1

    公开(公告)日：1998-05-28

    申请号：PCT/US1997021468

    申请日：1997-11-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

    IPC: H04L27/227

    CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

    Abstract: A digital communications DQPSK passband detector having a matched filter, a differential decoder, and a slicer that use elementary circuit components. In the matched filter, recovered carrier references signals are fed along with the received signal to a pair of XNOR gates. This arrangement effectively results in a multiplication operation without any complex circuit elements. The outputs of the XNOR gates control the direction of counting of a pair of binary counters that generate correlated values of the I and Q components in the received signal. Thus, the integrate/dump circuits of a conventional matched filter are replaced with simpler digital counters. A digital differential decoder to extract the phase difference information between two consecutive received symbols is built from a network of delay elements, multipliers, and adders to recover the phase data. The digital differential decoder produces a digital complex-signal output that can be quantized in a digital slicer to decode the plurality of binary bits transmitted through the data symbols. All these operations are performed on digital signals with basic digital circuit elements, thus resulting in a repeatable robust receiver design without complex hardware components.

    Abstract translation: 具有匹配滤波器的数字通信DQPSK通带检测器，差分解码器和使用基本电路部件的限幅器。 在匹配滤波器中，恢复的载波参考信号与接收信号一起馈送到一对XNOR门。 这种布置有效地导致没有任何复杂电路元件的乘法运算。 XNOR门的输出控制一对二进制计数器的计数方向，产生接收信号中I和Q分量的相关值。 因此，常规匹配滤波器的集成/转储电路被更简单的数字计数器代替。 从延迟元件，乘法器和加法器的网络构建用于提取两个连续的接收符号之间的相位差信息的数字差分解码器，以恢复相位数据。 数字差分解码器产生可在数字限幅器中量化的数字复信号输出，以对通过数据符号传输的多个二进制位进行解码。 所有这些操作都是用具有基本数字电路元件的数字信号执行的，从而导致可重复的鲁棒接收机设计，而无需复杂的硬件组件。

    AN IMPROVED PHASE DETECTOR FOR CARRIER RECOVERY IN A DQPSK RECEIVER
    3.
    发明申请
    AN IMPROVED PHASE DETECTOR FOR CARRIER RECOVERY IN A DQPSK RECEIVER 审中-公开
    用于DQPSK接收机中的载波恢复的改进的相位检测器

    公开(公告)号：WO1998023069A1

    公开(公告)日：1998-05-28

    申请号：PCT/US1997021467

    申请日：1997-11-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

    IPC: H04L27/227

    CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

    Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

    Abstract translation: 一种使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差的相位检测器。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈回路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较，以产生两个数字信号：接收信号的同相（I）和正交相位（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减少I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差并构造与该差成比例的相位误差信号来确定相位误差信号的大小。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。

    INTEGRATED CIRCUIT RESET INCORPORATING BATTERY MONITOR AND WATCHDOG TIMER
    4.
    发明申请
    INTEGRATED CIRCUIT RESET INCORPORATING BATTERY MONITOR AND WATCHDOG TIMER 审中-公开
    集成电路复位包含电池监视器和看门狗定时器

    公开(公告)号：WO1997024652A1

    公开(公告)日：1997-07-10

    申请号：PCT/US1996016463

    申请日：1996-10-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  SHELDON, Peter ,  SCHNIZLEIN, Paul ,  HENDRICKSON, Alan

    IPC: G06F01/24

    CPC classification number: G06F1/28 ,  G06F1/24 ,  G06F1/30 ,  G06F11/0757 ,  H03K17/22

    Abstract: A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

    Abstract translation: 公开了一种在集成电路中并入电池监视器和看门狗定时器的复位电路。 具有指示电池的充电状态的输出的电池监视器和具有指示由集成电路执行的软件的操作状态的输出的看门狗定时器被连接到具有复位信号输出的复位逻辑，其中复位逻辑产生 如果电池监视器输出或看门狗定时器输出有效，则复位信号输出上的复位信号。

    A CARRIER-RECOVERY LOOP WITH STORED INITIALIZATION IN A RADIO RECEIVER
    5.
    发明申请
    A CARRIER-RECOVERY LOOP WITH STORED INITIALIZATION IN A RADIO RECEIVER 审中-公开
    无线接收机存储初始化的载波恢复环路

    公开(公告)号：WO1998023036A1

    公开(公告)日：1998-05-28

    申请号：PCT/US1997021367

    申请日：1997-11-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  SCHNIZLEIN, Paul ,  BELL, Ed

    IPC: H03L07/14

    CPC classification number: H04L27/22 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/146 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/2273 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

    Abstract: A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers start to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initialization value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.

    Abstract translation: 具有促进循环初始化的特征的通信系统中的接收机的载波恢复回路。 载波恢复环路是使用反馈信号将恢复振荡器锁相到接收信号的载波的PLL。 在本发明中，将反馈信号的初始化值存储在存储器中并提供给数字控制的恢复振荡器（DCO）。 该初始化值使恢复的信号达到近似载波频率的初始频率。 当接收机开始与载波获取锁相时，载波恢复环路处于接近期望相位锁的状态。 以这种方式准备DCO对载体恢复循环有显着的改进。 环路获取锁相的响应时间部分取决于其与载波的初始频率偏移。 一般来说，减少初始偏移可以减少环路的采集时间。 通过这样预期载波的频率，该载波恢复回路可以具有改善的采集时间以达到锁相。 反馈信号的初始化值可以通过当载波恢复回路被锁相到接收信号时记录反馈信号的样本，或通过记录在板上的晶体振荡器来产生。 本发明还包括校正晶体振荡器频率漂移的机制。

    APPARATUS AND METHOD FOR PROTOCOL INTERFACE
    6.
    发明申请
    APPARATUS AND METHOD FOR PROTOCOL INTERFACE 审中-公开
    协议接口的设备和方法

    公开(公告)号：WO1997030540A1

    公开(公告)日：1997-08-21

    申请号：PCT/US1997001797

    申请日：1997-02-03

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  MULLINS, Jacqueline ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

    IPC: H04M01/72

    CPC classification number: H04M1/733 ,  H04M1/72502

    Abstract: An apparatus for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The apparatus comprises a radio interface connection with the frame formatter, for delivering and receiving the transmitted baseband signal and the received baseband signal, respectively, a FIFO/codec interface connected with the frame formatter, an interrupt interface connected with the frame formatter, a control register interface connected with the frame formatter, and a microcontroller interface connected with the frame formatter.

    Abstract translation: 一种用于数字无绳电信的装置包括用于逻辑信道格式化发送的基带信号和接收的基带信号的帧格式化器。 该装置包括与帧格式化器的无线电接口连接，用于分别传送和接收所发送的基带信号和接收的基带信号，与帧格式器连接的FIFO /编解码器接口，与帧格式化器连接的中断接口，控制 与帧格式器连接的寄存器接口，以及与帧格式器连接的微控制器接口。

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