公开(公告)号：WO2003058709A3

公开(公告)日：2003-07-17

申请号：PCT/US2002/039739

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KIM, UnSoon ,  SUN, Yu ,  KINOSHITA, Hiroyuki ,  CHANG, Kuo-Tung ,  SACHAR, Harpreet, K. ,  CHANG, Mark, S.

IPC: H01L21/762

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate (24) between active regions, and performing a double liner oxidation process and on the trenches. The method further includes performing a double sacrificial oxidation process and on the active regions, wherein corners (35) of the trenches are substantially rounded by the four oxidation processes.

公开(公告)号：WO2003058709A2

公开(公告)日：2003-07-17

申请号：PCT/US2002/039739

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KIM, UnSoon ,  SUN, Yu ,  KINOSHITA, Hiroyuki ,  CHANG, Kuo-Tung ,  SACHAR, Harpreet, K. ,  CHANG, Mark, S.

IPC: H01L21/762

CPC classification number: H01L21/76235

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches (34) into a silicon substrate (24) between active regions (30), and performing a double liner oxidation process (56) and (60) on the trenches (34). The method further includes performing a double sacrificial oxidation process (72) and (76) on the active regions (30), wherein corners (35) of the trenches (34) are substantially rounded by the four oxidation processes.

Abstract translation: 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽（34）蚀刻到有源区域（30）之间的硅衬底（24）中，并且在沟槽（34）上执行双衬层氧化工艺（56）和（60）。 该方法还包括在有源区域（30）上执行双重牺牲氧化工艺（72）和（76），其中沟槽（34）的拐角（35）通过四个氧化工艺基本上被圆化。

公开(公告)号：WO2007015987A3

公开(公告)日：2007-02-08

申请号：PCT/US2006/028506

申请日：2006-07-21

Applicant: SPANSION LLC ,  ADVANCED MICRO DEVICES, INC. ,  KIM, Unsoon ,  HUI, Angela, T. ,  WU, Yider ,  CHANG, Kuo-tung ,  KINOSHITA, Hiroyuki

Inventor： KIM, Unsoon ,  HUI, Angela, T. ,  WU, Yider ,  CHANG, Kuo-tung ,  KINOSHITA, Hiroyuki

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/105

Abstract: A method for forming a memory device ( 100) is provided. A nitride layer (330) is formed over a substrate (310). The nitride layer (330) and the substrate (310) are etched to form a trench (510). The nitride layer (330) is trimmed on opposite sides of the trench (510) to widen the trench (510) within the nitride layer (330). The trench (510) is filled with an oxide material (810). The nitride layer (330) is stripped from the memory device (100), forming a mesa (1410) above the trench (510).

公开(公告)号：WO2006108007A2

公开(公告)日：2006-10-12

申请号：PCT/US2006/012575

申请日：2006-04-04

Applicant: ADVANCED MICRO DEVICES, INC. ,  KIM, Unsoon ,  KINOSHITA, Hiroyuki ,  SUN, Yu ,  ACHUTHAN, Krishnaree ,  RAEDER, Christopher, H. ,  FOSTER, Christopher, M. ,  SACHAR, Harpreet, Kaur ,  SAHOTA, Kashmir, Singh

Inventor： KIM, Unsoon ,  KINOSHITA, Hiroyuki ,  SUN, Yu ,  ACHUTHAN, Krishnaree ,  RAEDER, Christopher, H. ,  FOSTER, Christopher, M. ,  SACHAR, Harpreet, Kaur ,  SAHOTA, Kashmir, Singh

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L21/762

CPC classification number: H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

Abstract: A method [300] is disclosed for the definition of the poly-1 layer [220] in a semiconductor wafer. A non-critical mask [227] is used to recess field oxides in the periphery [216] prior to poly-1 deposition [309] by an amount equal to the final poly-1 thickness [226]. A complimentary non-critical mask [222] is used to permit CMP [223] of the core [215] to expose the tops of core oxide mesas [225] from the shallow isolation trenches [210].

Abstract translation: 公开了用于半导体晶片中的多晶硅层[220]的定义的方法[300]。 使用非临界掩模[227]将聚-1沉积之前的周边[216]中的场氧化物凹入等于最终聚-1厚度的量[226]。 使用补充的非临界掩模[222]来允许芯[215]的CMP [223]从浅隔离沟[210]露出核心氧化物台面[225]的顶部。

公开(公告)号：WO2005048342A1

公开(公告)日：2005-05-26

申请号：PCT/US2004/033417

申请日：2004-10-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOPPER, Dawn, M. ,  KINOSHITA, Hiroyuki ,  WOO, Christy

Inventor： HOPPER, Dawn, M. ,  KINOSHITA, Hiroyuki ,  WOO, Christy

IPC: H01L21/768

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76865

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer (214) situated in a semiconductor die comprises a step of depositing a barrier layer (202) on sidewalls (206,207) of a contact hole (208) and on a native oxide layer (210) situated at a bottom of the contact hole (208), where the sidewalls (206,207) are defined by the contact hole (208) in a dielectric layer (204). The step of depositing (150) the barrier layer (202) on the sidewalls (206,207) of the contact hole (208) and on the native oxide layer (210) can be optimized such that the barrier layer (202) has a greater thickness at a top of the contact hole (208) than a thickness at the bottom of the contact hole (208). According to this exemplary embodiment, the method further comprises a step of removing (152) a portion (219) of the barrier layer (202) and the native oxide layer (210) situated at the bottom of the contact hole (208) to expose the silicide layer (214).

Abstract translation: 根据一个示例性实施例，用于在位于半导体管芯中的硅化物层（214）上形成接触的方法包括在接触孔（208）的侧壁（206,207）上沉积阻挡层（202）的步骤， 位于接触孔（208）的底部的天然氧化物层（210），其中侧壁（206,207）由电介质层（204）中的接触孔（208）限定。 可以优化将阻挡层（202）沉积在接触孔（208）的侧壁（206,207）上和在自然氧化物层（210）上的步骤，使得阻挡层（202）具有更大的厚度 在接触孔（208）的顶部处比接触孔（208）底部的厚度高。 根据该示例性实施例，该方法还包括去除（152）阻挡层（202）的部分（219）和位于接触孔（208）底部的自然氧化物层（210）暴露的步骤 硅化物层（214）。

公开(公告)号：EP1459374A2

公开(公告)日：2004-09-22

申请号：EP02806155.4

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KIM, UnSoon ,  SUN, Yu ,  KINOSHITA, Hiroyuki ,  CHANG, Kuo-Tung ,  SACHAR, Harpreet, K. ,  CHANG, Mark, S.

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/316

CPC classification number: H01L21/76235

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate (24) between active regions, and performing a double liner oxidation process and on the trenches. The method further includes performing a double sacrificial oxidation process and on the active regions, wherein corners (35) of the trenches are substantially rounded by the four oxidation processes.