公开(公告)号：WO2006108007A2

公开(公告)日：2006-10-12

申请号：PCT/US2006/012575

申请日：2006-04-04

Applicant: ADVANCED MICRO DEVICES, INC. ,  KIM, Unsoon ,  KINOSHITA, Hiroyuki ,  SUN, Yu ,  ACHUTHAN, Krishnaree ,  RAEDER, Christopher, H. ,  FOSTER, Christopher, M. ,  SACHAR, Harpreet, Kaur ,  SAHOTA, Kashmir, Singh

Inventor： KIM, Unsoon ,  KINOSHITA, Hiroyuki ,  SUN, Yu ,  ACHUTHAN, Krishnaree ,  RAEDER, Christopher, H. ,  FOSTER, Christopher, M. ,  SACHAR, Harpreet, Kaur ,  SAHOTA, Kashmir, Singh

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L21/762

CPC classification number: H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

Abstract: A method [300] is disclosed for the definition of the poly-1 layer [220] in a semiconductor wafer. A non-critical mask [227] is used to recess field oxides in the periphery [216] prior to poly-1 deposition [309] by an amount equal to the final poly-1 thickness [226]. A complimentary non-critical mask [222] is used to permit CMP [223] of the core [215] to expose the tops of core oxide mesas [225] from the shallow isolation trenches [210].

Abstract translation: 公开了用于半导体晶片中的多晶硅层[220]的定义的方法[300]。 使用非临界掩模[227]将聚-1沉积之前的周边[216]中的场氧化物凹入等于最终聚-1厚度的量[226]。 使用补充的非临界掩模[222]来允许芯[215]的CMP [223]从浅隔离沟[210]露出核心氧化物台面[225]的顶部。

公开(公告)号：WO2003030253A2

公开(公告)日：2003-04-10

申请号：PCT/US2002/030784

申请日：2002-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  SUN, Yu ,  CHANG, Chi

IPC: H01L21/8246

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

Abstract: Processes for doping and saliciding word lines (20) in a virtual ground array flash memory device without causing shorting between bit lines (26) are disclosed. According to one aspect, word lines (20) are doped prior to patterning the poly layer from which the word lines (20) are formed in the core region. Thereby, the poly layer protects the substrate between the word lines (20) from doping that could cause shorting between bit lines (26). According to another aspect, word lines (20) are exposed while spacer material, dielectric, or like material protects the substrate between word lines (20). The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines (26). Disclosed are virtual ground array flash memory devices with doped and salicided word lines (20), but no shorting between bit lines (26) even in virtual ground arrays where there are no oxide island isolation regions (28) between bit lines (26).

Abstract translation: 公开了在虚拟接地阵列闪存器件中掺杂和打字字线（20）而不导致位线（26）之间短路的过程。 根据一个方面，在对在芯区域中形成字线（20）的多晶层进行图案化之前，对字线（20）进行掺杂。 因此，多层保护字线（20）之间的衬底免受掺杂，这可能导致位线（26）之间的短路。 根据另一方面，字线（20）被露出，而隔离材料，电介质或类似材料在字线（20）之间保护衬底。 间隔物材料或电介质防止衬底以像掺杂那样在位线（26）之间引起短路的方式变得浸水。 公开了具有掺杂和含水字线（20）的虚拟接地阵列闪存器件，但即使在位线（26）之间没有氧化物岛隔离区域（28）的虚拟接地阵列中也不会在位线（26）之间发生短路。

公开(公告)号：WO2007047265A1

公开(公告)日：2007-04-26

申请号：PCT/US2006/039547

申请日：2006-10-06

Applicant: SPANSION LLC ,  ADVANCED MICRO DEVICES, INC. ,  YANG, Jean ,  SUN, Yu ,  RAMSBEY, Mark T. ,  WEIDONG, Qian ,  HUI, Angela T.

Inventor： YANG, Jean ,  SUN, Yu ,  RAMSBEY, Mark T. ,  WEIDONG, Qian ,  HUI, Angela T.

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method for performing a bit line implant is disclosed. The method includes forming a group of structures (1410) on an oxide-nitride-oxide stack (1220, 1230, 1240) of a semiconductor device (1200). Each structure of the group of structures includes a polysilicon portion (1250) and a hard mask portion (1260). A first structure (1410) of the group of structures is separated from a second structure (1410) of the group of structures by less than 100 nanometers. The method further includes using the first structure (1410) and the second structure (1410) to isolate a portion of the semiconductor device (1200) for the bit line implant.

Abstract translation: 公开了一种用于执行位线植入的方法。 该方法包括在半导体器件（1200）的氧化物 - 氮化物 - 氧化物堆叠（1220,1230,1240）上形成一组结构（1410）。 该组结构的每个结构包括多晶硅部分（1250）和硬掩模部分（1260）。 该组结构的第一结构（1410）与该组结构的第二结构（1410）分开小于100纳米。 该方法还包括使用第一结构（1410）和第二结构（1410）来隔离位线植入物的半导体器件（1200）的一部分。

公开(公告)号：WO2003088353A1

公开(公告)日：2003-10-23

申请号：PCT/US2003/004461

申请日：2003-02-14

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： RAMSBEY, Mark, T. ,  KAMAL, Tazrien ,  YANG, Jean, Y. ,  LINGUNIS, Emmanuil ,  SHIRAIWA, Hidehiko ,  SUN, Yu

IPC: H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate (506) having a core region (502) and a periphery region (504). A charge-trapping dielectric layer (510) is deposited in the core region (502), and a gate dielectric layer (522) is deposited in the periphery region (504). Bitlines (518) are formed in the semiconductor substrate (506) in the core region (502) and not in the periphery region (504). A wordline-gate layer (524) is formed and implanted with dopant in the core region (502) and not in the periphery region (504). A wordline (528) and gate (530) are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate (506) around the gate (530), and the gate (530) is implanted with a gate doping implantation in the periphery region (504) and not in the core region (502).

Abstract translation: 集成电路的制造方法具有芯部区域（502）和外围区域（504）的半导体基板（506）。 在芯区域（502）中沉积电荷捕获介电层（510），并且在周边区域（504）中沉积栅介质层（522）。 位线（518）形成在芯区域（502）中的半导体衬底（506）中，而不是在周边区域（504）中。 在芯区域（502）中而不是周边区域（504）中形成并注入掺杂剂的字线栅层（524）。 形成字线（528）和门（530）。 在半导体衬底（506）中围绕栅极（530）注入掺杂剂源极/漏极结，栅极（530）在外围区域（504）而不是在核心区域（502）中注入栅极掺杂注入 ）。

公开(公告)号：WO2003030230A1

公开(公告)日：2003-04-10

申请号：PCT/US2002/013578

申请日：2002-04-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WU, Yider ,  KIM, UnSoon ,  SUN, Yu ,  YANG, Jean, Yee-Mei

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/11517

Abstract: A method for transferring a reduced lithographic image size pattern onto a film (14) on a substrate (12) is disclosed. A photosensitive material having an opening (20) of a minimum size achievable by the limits of lithography is transferred onto a mask layer (16) on a substrate (12) having a film (14) thereon. Reduction in the image size is achieved by establishing sidewalls (28) to the interior vertical surfaces (26) of the opening of the mask layer (16) by depositing a conformal layer (28), followed by anisotropic etching. The dimension of the opening (24) is reduced by the combined thickness of the two opposite sidewalls (28). An anisotropic etching of the film (14) transfers a pattern of openings (30) of a minimum size smaller than possible by lithography.

Abstract translation: 公开了一种将还原的平版印刷图像尺寸图案转印到基片（12）上的薄膜（14）上的方法。 具有通过光刻限制可实现的最小尺寸的开口（20）的感光材料被转印到其上具有膜（14）的基底（12）上的掩模层（16）上。 通过沉积保形层（28），然后进行各向异性蚀刻，通过将掩模层（16）的开口的内部垂直表面（26）建立侧壁（28）来实现图像尺寸的减小。 开口（24）的尺寸减小了两个相对侧壁（28）的组合厚度。 薄膜（14）的各向异性蚀刻通过光刻传递尺寸小于可能的最小尺寸的开口（30）图案。

公开(公告)号：WO2003003460A2

公开(公告)日：2003-01-09

申请号：PCT/US2001/049056

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  FLIESLER, Michael ,  RANDOLPH, Mark ,  QIAN, Mimi ,  SUN, Yu

IPC: H01L27/02

CPC classification number: H01L29/7833 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the present invention provides a process for forming IC devices (100) with ESD protection transistors (112). According to one aspect of the invention, an ESD protection transistor (112) is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors (112) that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device (100).

Abstract translation: 本发明的一个方面提供一种用于形成具有ESD保护晶体管（112）的IC器件（100）的工艺。 根据本发明的一个方面，ESD保护晶体管（112）具有轻掺杂，然后在形成间隔物之后进行重掺杂。 具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。 因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管（112）。 间隔物可以与其它晶体管的间隔物同时形成，例如器件（100）的外围区域中的其它晶体管。

公开(公告)号：WO2003032393A2

公开(公告)日：2003-04-17

申请号：PCT/US2002/031330

申请日：2002-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUN, Yu ,  VAN BUSKIRK, Michael, A. ,  RAMSBEY, Mark, T.

IPC: H01L27/105

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric (114) over a substrate (112); forming a first set of memory cell gates (116) over the charge trapping dielectric (114) in a core region; forming a conformal insulation material layer (118) around the first set of memory cell gates (116); and forming a second set of memory cell gates (122) in the core region, wherein each memory cell gate of the second set of memory cell gates (122) is adjacent to at least one memory cell gate of the first set of memory cell gates (116), each memory cell gate of the first set of memory cell gates (116) is adjacent at least one memory cell gate of the second set of memory cell gates (122), and the conformal insulation material layer (118) is positioned between each adjacent memory cell gate is disclosed.

Abstract translation: 一种形成非易失性半导体存储器件的方法，包括在衬底（112）上方形成电荷俘获电介质（114）; 在核心区域中的所述电荷俘获电介质（114）上方形成第一组存储器单元栅极（116） 围绕所述第一组存储器单元栅极（116）形成共形绝缘材料层（118）; 以及在核心区域中形成第二组存储器单元栅极（122），其中第二组存储器单元栅极（122）中的每一存储器单元栅极与第一组存储器单元栅极（122）中的至少一个存储器单元栅极相邻 （116）中，所述第一组存储器单元栅极（116）的每个存储器单元栅极与所述第二组存储器单元栅极（122）中的至少一个存储器单元栅极相邻，并且所述共形绝缘材料层（118）被定位 在每个相邻的存储单元门之间被公开。

公开(公告)号：WO2003003460A3

公开(公告)日：2003-01-09

申请号：PCT/US2001/049056

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  FLIESLER, Michael ,  RANDOLPH, Mark ,  QIAN, Mimi ,  SUN, Yu

IPC: H01L27/02

Abstract: One aspect of the present invention provides a process for forming IC devices (100) with ESD protection transistors (112). According to one aspect of the invention, an ESD protection transistor (112) is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors (112) that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device (100).

公开(公告)号：WO1997049089A1

公开(公告)日：1997-12-24

申请号：PCT/US1997005218

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

Abstract translation: 本发明有助于编程所选择的浮动栅极器件，同时成功地禁止对未选择器件的编程，而不需要生长多个厚度的氧化物。 本发明的优选实施例利用多选择栅极器件。 特别地，选择栅极器件优选地是双浮置栅极器件，而不是在当前闪存存储器系统中用作选择栅极器件的常规晶体管（或用作常规晶体管的器件）。

公开(公告)号：WO2003063168A3

公开(公告)日：2003-07-31

申请号：PCT/US2002/040823

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHEN, Pau-Ling ,  VANBUSKIRK, Michael, A. ,  SUN, Yu

IPC: G11C16/26

Abstract: A system (600, 800) is disclosed for producing an indication (679) of the logical state of a flash memory cell (866) for virtual ground flash memory (640) operations. The system (600, 800) comprises a bit line precharge and hold circuit (660, 855) which is operable to apply and maintain a source terminal voltage (859) ( e.g. , about 0 volts, ground) to a bit line (850) associated with the source terminal (857) of a cell adjacent (856) to the cell which is sensed (866) during a read operation, wherein the applied source terminal voltage is substantially the same as the bit line virtual ground voltage (869) applied to the source terminal bit line (860) of the selected memory cell (866) to be sensed. The system (600, 800) also includes a drain bit line circuit (650, 875) operable to generate a drain terminal voltage (615, 815) for a drain terminal (868) of a selected memory cell (866) to be sensed. The system (600, 800) further includes a selective bit line decode circuit (652) which is operable to select the bit lines (860, 870) of a memory cell (866) to be sensed and the bit line (850) of an adjacent cell (856), and a core cell sensing circuit (695, 890) which is operable to sense a core cell sense current (675) at a bit line associated with a source terminal (867) of the selected memory cell (866) to be sensed during memory read operations, and produce an indication (679) of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.