公开(公告)号：WO1996029796A1

公开(公告)日：1996-09-26

申请号：PCT/US1996000694

申请日：1996-01-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CRAYFORD, Ian, S. ,  LO, William

IPC: H04L12/22

CPC classification number: H04L43/00 ,  H04L12/22 ,  H04L12/44 ,  H04L12/4625 ,  H04L43/0817 ,  H04L63/0272

Abstract: A method for providing a secure local area network includes the steps of receiving a data packet having a destination address and comparing the destination address to stored end station addresses. The data packet is disrupted on the repeater (12) for the ports except the port with an associated stored end station address matching the destination address. Also, the disrupting of the data packet can be enabled on an individual port basis. A system includes a controller (104), a memory/comparator (102), and an inverse disrupt control mechanism (108). The inverse disrupt control mechanism produces a disrupt signal to disrupt the data packet on non-matching ports of the repeater when a match occurs within the repeater. The data packet is not disrupted on a port linking two repeaters when there is no match within the repeater. The inverse disrupt control can also be enabled or disabled on an individual port basis.

Abstract translation: 一种用于提供安全局域网的方法包括以下步骤：接收具有目的地地址的数据分组，并将目的地地址与存储的终端地址进行比较。 数据包在中继器（12）上对于除了具有与目的地地址匹配的相关联的存储的终端站地址的端口之外的端口被中断。 此外，可以在单个端口上启用数据分组的中断。 系统包括控制器（104），存储器/比较器（102）和反向中断控制机构（108）。 当中继器发生匹配时，逆中断控制机制产生中断信号，以中断中继器的非匹配端口上的数据包。 当中继器中没有匹配时，数据包在连接两个中继器的端口上不会中断。 也可以在单个端口上启用或禁用反向中断控制。

公开(公告)号：WO1996021299A1

公开(公告)日：1996-07-11

申请号：PCT/US1995015297

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian

IPC: H04L12/18

CPC classification number: H04L63/0236 ,  H04L12/1886 ,  H04L12/22 ,  H04L12/44

Abstract: A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, multicast response. A multicast controller (70x) receives a multicast identifier extracted from a destination address field of a data packet. A plurality of memories, one associated with each port (85x), determines the associated ports response to the multicast identifier. Each memory stores a multicast control code. When the multicast control code for a particular port has a value indicating that the associated port is enabled to receive multicast packets, assertion of the multicast identifier to the multicast controller for the particular port results in disabling the security masking for the port and subsequent transmission of unmodified data from the particular port.

Abstract translation: 实现数据包掩蔽的安全中继器包括基于每端口的可编程和选择性的多播响应。 多播控制器（70x）接收从数据包的目的地地址字段提取的多播标识符。 与每个端口（85x）相关联的多个存储器确定相关端口对多播标识符的响应。 每个存储器存储组播控制代码。 当特定端口的组播控制代码具有指示关联的端口被允许接收多播分组的值时，将特定端口的组播标识符断言给组播控制器导致禁用该端口的安全掩蔽并随后传输 来自特定端口的未修改数据。

公开(公告)号：WO1996029801A1

公开(公告)日：1996-09-26

申请号：PCT/US1996000693

申请日：1996-01-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian, S.

IPC: H04L12/44

CPC classification number: H04L43/00 ,  H04L12/44

Abstract: A method and apparatus for efficiently transferring a data packet on a network. The efficient transfer of data includes compressing the data as the data packet is transmitted from a repeater (12) to a management unit (10). The method determines if a destination address of a received packet matches a stored management unit address. When the stored address does not match the destination address, the data packet is compressed. The apparatus includes a repeater, a management unit, and a packet compression mechanism (26). The apparatus further includes comparator circuit means (38, 44) for determining address comparisons and count comparisons to control data compression.

Abstract translation: 一种用于在网络上有效地传送数据分组的方法和装置。 数据的有效传输包括当数据分组从中继器（12）发送到管理单元（10）时压缩数据。 该方法确定接收到的分组的目的地址是否与存储的管理单元地址匹配。 当存储的地址与目标地址不匹配时，数据包被压缩。 该装置包括中继器，管理单元和分组压缩机构（26）。 该装置还包括用于确定地址比较和计数比较以控制数据压缩的比较器电路装置（38,44）。

公开(公告)号：WO1996015608A1

公开(公告)日：1996-05-23

申请号：PCT/US1995013526

申请日：1995-10-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William

IPC: H04L12/44

CPC classification number: H04L12/44 ,  H04L12/46 ,  H04L45/7453 ,  Y10S370/911

Abstract: In a managed repeater (10) having an address learn capability wherein receipt at a particular port (30) of a data packet having a received source address different from a stored source address associated with the particular port replaces the stored source address with the received source address, a source address locking circuit includes an address learn circuit associated with the particular port, for replacing the stored source address with the received source address when the stored source address does not match the received source address, and an address lock register for the particular port, coupled to the address learn circuit, for storing a bit value to disable the address learn circuit from replacing the stored source address with the received source address. This managed repeater provides improved security in a network having source address updating by allowing an administrator to disable the source address update for a particular port in the managed repeater. Each address lock register is externally programmable, and the administrator is able to program time windows to disable source address updating for a particular port. The administrator may program each address lock register independently to prevent the stored source address associated with each port from being updated. The managed repeater allows the administrator to determine on a per port basis whether the managed repeater's address learning capability should be enabled or disabled for a programmable time window.

Abstract translation: 在具有地址学习能力的托管中继器（10）中，其中在具有与存储的与特定端口相关联的源地址不同的接收到的源地址的数据分组的特定端口（30）处的接收将所存储的源地址替换为所接收的源 源地址锁定电路包括与特定端口相关联的地址学习电路，用于当存储的源地址与接收到的源地址不匹配时用存储的源地址替换存储的源地址，以及用于特定端口的地址锁定寄存器 端口，耦合到地址学习电路，用于存储位值以禁用地址学习电路用接收到的源地址替换存储的源地址。 该托管中继器通过允许管理员禁用托管中继器中的特定端口的源地址更新来提供具有源地址更新的网络中的改进的安全性。 每个地址锁定寄存器是外部可编程的，管理员能够编程时间窗口来禁用特定端口的源地址更新。 管理员可以独立编程每个地址锁定寄存器，以防止与每个端口相关联的存储的源地址被更新。 托管中继器允许管理员在每个端口基础上确定在可编程时间窗口中是否启用或禁用托管中继器的地址学习能力。

公开(公告)号：WO1996015607A1

公开(公告)日：1996-05-23

申请号：PCT/US1995013525

申请日：1995-10-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William

IPC: H04L12/44

CPC classification number: H04L43/00 ,  H04L43/0811 ,  H04L43/0817 ,  H04L49/351 ,  H04L49/40

Abstract: Apparatus and method for simply, efficiently and economically accessing every media attachment unit (MAU) (115) management information base (MIB) in a managed repeater (100). MAU MIBs pass through a repeater to a management unit (110) that accesses the repeater for all of the MAU MIBs, in addition to the repeater MIB. Conversely, the management unit passes MAU control information to the MAUs through the repeater. Because all the MIBs in the managed repeater are accessed through the single device, a simple microprocessor interface is used to connect the repeater to the management unit. Also, the managed repeater signals, by generation of an interrupt for example, any changes in the MAU MIB to the management unit. In addition, the management unit easily determines which MAU caused a particular interrupt because all interrupt status signals are consolidated into registers in the repeater. The status signals are stored in a particular format to assist identification of status conditions for particular MAUs.

Abstract translation: 用于简单，有效和经济地访问被管理中继器（100）中的每个媒体附着单元（MAU）（115）管理信息库（MIB）的装置和方法。 除了中继器MIB之外，MAU MIB通过中继器到达访问所有MAU MIB的中继器的管理单元（110）。 相反，管理单元通过中继器将MAU控制信息传递给MAU。 由于托管中继器中的所有MIB都通过单个设备访问，所以使用简单的微处理器接口将中继器连接到管理单元。 而且，被管理的中继器通过产生例如中断的MAU MIB向管理单元发送任何改变。 此外，管理单元容易确定哪个MAU引起特定中断，因为所有中断状态信号都被合并到中继器中的寄存器中。 状态信号以特定格式存储以帮助识别特定MAU的状态条件。

公开(公告)号：WO1996038949A1

公开(公告)日：1996-12-05

申请号：PCT/US1996004663

申请日：1996-04-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian

IPC: H04L12/22

CPC classification number: H04L63/02 ,  H04L12/22 ,  H04L12/44 ,  H04L12/4625

Abstract: A secure repeater (20) implementing data packet masking includes a programmable and selective, on a per port basis, disrupt response responsive to any of several selectable qualifying conditions. A disrupt controller (70) receives signals indicating various characteristics of fields of a data packet, and other conditions. A register bank (76) includes a plurality of memories, one associated with each port and some of the conditions, assists the disrupt controller to determine the associated port's disrupt response to the data packet. Each memory stores a disrupt control code. When the disrupt control code for a particular port has a value indicating that the associated port is enabled, deassertion of a condition signal associated with that control code results in disruption of a data packet. A cell array (200) permits simple, efficient scaling and formation of integrated semiconductor structures to implement complex disrupt logic equations.

Abstract translation: 实现数据分组屏蔽的安全中继器（20）包括在每个端口基础上的可编程和选择性响应于若干可选择的条件条件中的任何一个的中断响应。 中断控制器（70）接收指示数据分组的各种特性的信号以及其他条件。 寄存器组（76）包括多个存储器，一个与每个端口相关联的存储器和一些条件，帮助中断控制器确定相关端口对数据包的中断响应。 每个存储器存储中断控制代码。 当特定端口的中断控制代码具有指示相关端口被使能的值时，与该控制代码相关联的条件信号的取消取消导致数据分组的中断。 单元阵列（200）允许简单，有效地缩放和形成集成半导体结构以实现复杂的中断逻辑方程。

公开(公告)号：WO1996015606A1

公开(公告)日：1996-05-23

申请号：PCT/US1995013498

申请日：1995-10-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William

IPC: H04L12/26

CPC classification number: H04L43/0847

Abstract: A circuit including a data formatter (70) for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory (80), a memory for storing the desired information for later access by a microprocessor (20), and a controller (90) for selectively transferring and writing the desired information from the data formatter to said memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure. The present invention has an advantage of being more efficient and economical in gathering error statistics of data packets, as well as providing an increased capability to determine sophisticated error statistics on a packet-by-packet basis.

Abstract translation: 一种包括数据格式化器（70）的电路，用于接收与数据分组相关联的期望信息并将这些比特排列成用于传送到存储器（80）的格式;存储器，用于存储所需要的信息以供稍后由微处理器（20）访问， 以及用于从所述数据格式化器向所述存储器选择性地传送和写入所需信息的控制器（90）。 该电路通过仅存储具有错误的数据分组的期望信息来提供改进的性能。 也就是说，数据分组本身内部的信息，诸如源地址，以及诸如中继器端口号之类的数据分组外的信息，除了诸如错误条件的数据分组错误信息之外，可以被存储为 微处理器在其休闲时读取的存储器中的错误统计量。 本发明具有在收集数据分组的错误统计方面更有效和经济的优点，并且提供了逐个分组的基础上增加确定复杂错误统计的能力。

公开(公告)号：WO1996015605A1

公开(公告)日：1996-05-23

申请号：PCT/US1995013355

申请日：1995-10-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  MCROBERT, Stephen

IPC: H04L12/26

CPC classification number: H04L43/0817 ,  G09G3/14

Abstract: An interface to an indicator array (25) for providing status information from a repeater (20) used in a computer network (10). The interface multiplexes status value signals from the repeater provided to a group of enabled source buffers (55) driving columns of the array. Rows of the array are driven by status enable signals from a sink buffer (70) attached to each row. LEDs (30) of the array have an anode connected to a source buffer and a cathode connected to a sink buffer. Cycling through the source buffer groups and status enable signals provides a 10 % duty cycle for each indicator. When status values change more frequently than about once per millisecond, a pulse stretcher is used to extend the perceived duration of the status indication.

Abstract translation: 指示器阵列（25）的接口，用于从在计算机网络（10）中使用的中继器（20）提供状态信息。 该接口将提供的转发器的状态值信号复用到驱动阵列的一组启用的源缓冲器（55）。 阵列的行由附加到每一行的接收缓冲器（70）的状态使能信号驱动。 阵列的LED（30）具有连接到源缓冲器的阳极和连接到宿缓冲器的阴极。 循环通过源缓冲组和状态使能信号为每个指示器提供10％的占空比。 当状态值比每毫秒更频繁地改变大约一次时，脉冲展开器用于延长状态指示的感知持续时间。

公开(公告)号：WO1996029797A1

公开(公告)日：1996-09-26

申请号：PCT/US1996000695

申请日：1996-01-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CRAYFORD, Ian, S. ,  LO, William

IPC: H04L12/26

CPC classification number: H04L43/00 ,  H04L12/44 ,  H04L43/0847 ,  H04Q2213/13172 ,  H04Q2213/13293 ,  H04Q2213/13396

Abstract: A method and system for providing statistical network information carried in a data packet (8) being transmitted on a network. The method includes the steps of receiving a data packet having a data portion on a repeater (12) and transferring the data portion to a management unit (10). The method further includes the step of appending statistical information to the data portion during an inter-packet gap period. The apparatus for increasing information in a data packet on a network includes a repeater mechanism, a management unit mechanism, and a packet tagging circuit. The repeater mechanism receives a data packet having a data portion, the management unit mechanism determines statistical information based on the data packet, and the packet tagging circuit appends information to the data portion of the data packet during an inter-packet gap period.

Abstract translation: 一种用于提供在网络上发送的数据分组（8）中承载的统计网络信息的方法和系统。 该方法包括以下步骤：在中继器（12）上接收具有数据部分的数据分组，并将数据部分传送到管理单元（10）。 该方法还包括在数据包间隔时段期间将统计信息附加到数据部分的步骤。 用于增加网络中的数据分组中的信息的装置包括中继器机制，管理单元机制和分组标签电路。 中继器机构接收具有数据部分的数据分组，管理单元机构基于数据分组确定统计信息，分组标签电路在分组间间隔时段期间将信息附加到数据分组的数据部分。

公开(公告)号：WO1996021300A1

公开(公告)日：1996-07-11

申请号：PCT/US1995014638

申请日：1995-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian

IPC: H04L12/22

CPC classification number: H04L12/44 ,  B60G17/0182 ,  B60G2400/102 ,  B60G2400/202 ,  B60G2600/182 ,  B60G2600/1872 ,  B60G2600/1873 ,  B60G2800/162 ,  H04L12/22 ,  H04L63/0236

Abstract: A secure repeater (20) implementing data packet masking includes a programmable and selective, on a per port basis, delay disrupt response. A delay disrupt controller (70) receives signals indicating retransmissions of fields from a data packet. These signals include a destination address field and a source address field. A plurality of memories, one associated with each port, determines the associated port's delay response to the data packet. Each memory stores a delay disrupt control code. When the delay disrupt control code for a particular port has a value indicating that the associated port is enabled to delay disruption of a data packet, security marking is disabled until the source address field is retransmitted from the particular port.

Abstract translation: 实现数据包掩蔽的安全中继器（20）包括在每个端口的可编程和选择性的延迟中断响应。 延迟中断控制器（70）从数据包接收指示字段重传的信号。 这些信号包括目的地址字段和源地址字段。 与每个端口相关联的多个存储器确定相关端口对数据分组的延迟响应。 每个存储器存储一个延迟中断控制码。 当延迟中断特定端口的控制代码具有指示相关端口被使能以延迟数据分组中断的值时，安全标记被禁用，直到源地址字段从特定端口重传为止。