公开(公告)号：WO2006118799A1

公开(公告)日：2006-11-09

申请号：PCT/US2006/014781

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  BIERSTEDT, Helmut ,  LUNING, Scott, D.

Inventor： KAMMLER, Thorsten ,  BIERSTEDT, Helmut ,  LUNING, Scott, D.

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L29/7833 ,  H01L21/0206 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78621

Abstract: A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

Abstract translation: 第一栅极结构和第二栅极结构形成在半导体衬底上。 第一保护层形成在第一栅极结构和相关源极漏极区之上。 在去除第一保护层之前，在第二源极漏极上形成第一外延层。

公开(公告)号：WO2006137963A1

公开(公告)日：2006-12-28

申请号：PCT/US2006/014696

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  BROWN, David, E. ,  EN, William, George ,  KAMMLER, Thorsten ,  BESSER, Paul, R. ,  LUNING, Scott, D.

Inventor： BROWN, David, E. ,  EN, William, George ,  KAMMLER, Thorsten ,  BESSER, Paul, R. ,  LUNING, Scott, D.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling suicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent control of the placement of these features for optimizing device performance. The methodology utilizes multiple spacers to decrease current crowding effects in devices due to proximity effects between LDD and deep S/D regions in reduced architecture devices.

Abstract translation: 提出了集成方案，其提供了相对于选择性外延生长（SEG）引发的S / D区域去耦合深源/漏（S / D）植入物的放置，以及相对于升高的S / D去耦自杀放置 特征。 这些集成方案可以以多种方式组合，以允许独立控制这些特征的放置以优化装置性能。 该方法利用多个间隔物来减少由于减少的架构设备中LDD与深S / D区域之间的邻近效应而导致的器件中的电流拥挤效应。

公开(公告)号：WO2002075781A2

公开(公告)日：2002-09-26

申请号：PCT/US2002/002774

申请日：2002-02-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PELLERIN, John, G. ,  CHEEK, Jon, D. ,  DAWSON, Robert ,  HAUSE, Frederick, N. ,  LUNING, Scott, D.

IPC: H01L

CPC classification number: H01L29/66507 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/6653

Abstract: A transistor, comprising a semiconducting substrate (30), a gate insulation layer (48) positioned above the substrate (30), agate electrode (46) positioned above the gate insulation layer (48), a plurality of source/drain regions formed in the substrate (30), a first (40A) and a second (52) sidewall spacer positioned adjacent the gate electrode (46), and a metal silicide layer (54) formed above each of the source/drain regions, a portion of the metal silicide layer (54) being positioned adjacent the first sidewall spacer (40A) and under the second sidewall spacer (52). The method comprises forming a transistor by forming a gate insulation layer (48) and a gate electrode (46) above a semiconducting substrate (30), forming a first sidewall spacer (40A) adjacent the gate electrode (46), forming a metal silicide layer (50) adjacent the first sidewall spacer (40A) and above previously formed implant regions in the substrate, forming a second sidewall spacer (52) above a portion of the metal silicide layer (50) and adjacent the first sidewall spacer (40A), and forming additional metal silicide material (50A) above the metal silicide layer (50) extending beyond the second sidewall spacer (52).

Abstract translation: 一种晶体管，包括半导体衬底（30），位于衬底（30）上方的栅极绝缘层（48），位于栅极绝缘层（48）上方的玛瑙电极（46），多个源极/漏极区域 基板（30），邻近栅电极（46）定位的第一（40A）和第二（52）侧壁间隔物，以及形成在每个源极/漏极区域上方的金属硅化物层（54） 金属硅化物层（54）定位成邻近第一侧壁间隔物（40A）并位于第二侧壁间隔物（52）下方。 该方法包括通过在半导体衬底（30）上形成栅极绝缘层（48）和栅电极（46）来形成晶体管，形成邻近栅电极（46）的第一侧壁间隔物（40A），形成金属硅化物 邻近第一侧壁间隔物（40A）的层（50）以及衬底中先前形成的注入区域，在金属硅化物层（50）的一部分上方并邻近第一侧壁间隔物（40A）形成第二侧壁间隔物（52） 并且在金属硅化物层（50）之上形成延伸超过第二侧壁间隔物（52）的附加金属硅化物材料（50A）。

公开(公告)号：EP1040486A1

公开(公告)日：2000-10-04

申请号：EP98964761.5

申请日：1998-12-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SOBEK, Daniel ,  THURGATE, Timothy, James ,  LUNING, Scott, D. ,  CHAN, Vei-Han ,  HADDAD, Sameer, S.

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

公开(公告)号：EP1040486B1

公开(公告)日：2002-02-27

申请号：EP98964761.5

申请日：1998-12-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SOBEK, Daniel ,  THURGATE, Timothy, James ,  LUNING, Scott, D. ,  CHAN, Vei-Han ,  HADDAD, Sameer, S.

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.