公开(公告)号：WO2003098685A1

公开(公告)日：2003-11-27

申请号：PCT/US2002/040500

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  CHEEK, Jon, D.

IPC: H01L21/8234

CPC classification number: H01L21/823462

Abstract: In one illustrative embodiment, the method comprises forming a sacrificial layer of material (34) above a substrate (30) comprised of silicon, performing a wet etching process to remove the sacrificial layer (34), implanting fluorine atoms into selected portions of the substrate (30) after the sacrificial layer (34) is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers (42, 44) above the substrate (30), the gate insulation layers (42) formed above the fluorine implanted selected portions of the substrate (30) having a thickness that is greater than a thickness of the gate insulation layers (44) formed above portions of the substrate (30) not implanted with fluorine.

Abstract translation: 在一个说明性实施例中，该方法包括在由硅构成的衬底（30）上形成材料牺牲层（34），执行湿蚀刻工艺以去除牺牲层（34），将氟原子注入衬底的选定部分 （30），在所述牺牲层（34）被去除之后，进行热氧化处理以在所述基板（30）上方形成多个栅极绝缘层（42,44），所述栅极绝缘层（42）形成在氟 植入衬底（30）的选定部分的厚度大于未注入氟的衬底（30）的部分上方形成的栅极绝缘层（44）的厚度。

公开(公告)号：WO2002075781A2

公开(公告)日：2002-09-26

申请号：PCT/US2002/002774

申请日：2002-02-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PELLERIN, John, G. ,  CHEEK, Jon, D. ,  DAWSON, Robert ,  HAUSE, Frederick, N. ,  LUNING, Scott, D.

IPC: H01L

CPC classification number: H01L29/66507 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/6653

Abstract: A transistor, comprising a semiconducting substrate (30), a gate insulation layer (48) positioned above the substrate (30), agate electrode (46) positioned above the gate insulation layer (48), a plurality of source/drain regions formed in the substrate (30), a first (40A) and a second (52) sidewall spacer positioned adjacent the gate electrode (46), and a metal silicide layer (54) formed above each of the source/drain regions, a portion of the metal silicide layer (54) being positioned adjacent the first sidewall spacer (40A) and under the second sidewall spacer (52). The method comprises forming a transistor by forming a gate insulation layer (48) and a gate electrode (46) above a semiconducting substrate (30), forming a first sidewall spacer (40A) adjacent the gate electrode (46), forming a metal silicide layer (50) adjacent the first sidewall spacer (40A) and above previously formed implant regions in the substrate, forming a second sidewall spacer (52) above a portion of the metal silicide layer (50) and adjacent the first sidewall spacer (40A), and forming additional metal silicide material (50A) above the metal silicide layer (50) extending beyond the second sidewall spacer (52).

Abstract translation: 一种晶体管，包括半导体衬底（30），位于衬底（30）上方的栅极绝缘层（48），位于栅极绝缘层（48）上方的玛瑙电极（46），多个源极/漏极区域 基板（30），邻近栅电极（46）定位的第一（40A）和第二（52）侧壁间隔物，以及形成在每个源极/漏极区域上方的金属硅化物层（54） 金属硅化物层（54）定位成邻近第一侧壁间隔物（40A）并位于第二侧壁间隔物（52）下方。 该方法包括通过在半导体衬底（30）上形成栅极绝缘层（48）和栅电极（46）来形成晶体管，形成邻近栅电极（46）的第一侧壁间隔物（40A），形成金属硅化物 邻近第一侧壁间隔物（40A）的层（50）以及衬底中先前形成的注入区域，在金属硅化物层（50）的一部分上方并邻近第一侧壁间隔物（40A）形成第二侧壁间隔物（52） 并且在金属硅化物层（50）之上形成延伸超过第二侧壁间隔物（52）的附加金属硅化物材料（50A）。

公开(公告)号：WO2005093825A1

公开(公告)日：2005-10-06

申请号：PCT/US2005/006177

申请日：2005-02-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  BONSER, Douglas, J. ,  GROSCHOPF, Johannes ,  DAKSHINA-MURTHY, Srikanteswara ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

Inventor： BONSER, Douglas, J. ,  GROSCHOPF, Johannes ,  DAKSHINA-MURTHY, Srikanteswara ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer (52), e.g., no thicker than 400Å. The very thin nitride polish stop layer (52) is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions (80), and is removed prior to gate oxide (101) and gate electrode (100) formation.

Abstract translation: 通过使用非常薄的氮化物抛光停止层（52）（例如不大于400）来消除或基本上减少STI形成。 在随后的掩模，植入和清洁步骤中，非常薄的氮化物抛光停止层（52）被保持就位以形成掺杂剂区域（80），并且在形成栅极氧化物（101）和栅电极（100）之前被去除。

公开(公告)号：WO2005053035A1

公开(公告)日：2005-06-09

申请号：PCT/US2004/033413

申请日：2004-10-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  PAN, James, N. ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

Inventor： PAN, James, N. ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/78639

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions (15) are provided on a substrate (12) with a gate electrode (16) formed on the uppermost channel region (15), separated by a gate oxide (14c), for example. The vertical stacking of multiple channels (15) and the gate electrode (16) permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract translation: 多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。 多个通道区域（15）设置在基板（12）上，其栅极电极（16）形成在最上通道区域（15）上，例如由栅极氧化物（14c）分开。 多个通道（15）和栅电极（16）的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

公开(公告)号：WO2006062796A3

公开(公告)日：2006-06-15

申请号：PCT/US2005/043398

申请日：2005-11-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  WAITE, Andrew, Michael ,  CHEEK, Jon, D.

Inventor： WAITE, Andrew, Michael ,  CHEEK, Jon, D.

IPC: H01L21/762

Abstract: A semiconductor device comprising a substrate 18 having a first crystal orientation is provided. A first insulating layer 14 overlies the substrate 18 and a plurality of silicon layers overlie the first insulating layer 14. A first silicon layer 42 comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer 25 comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer 42. Because holes have higher mobility in the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided. A silicon-on-insulator structure comprising a first silicon substrate 18 having a first crystal orientation with a first insulating layer 14 formed thereon and a first silicon layer 19 having a second crystal orientation and a crystal plane overlying the first insulating layer 14 is bonded to a second silicon substrate 20. The second silicon substrate 20 has the second crystal orientation and a crystal plane and a second insulating layer 24 formed thereon. The second silicon substrate 20 comprises a line of defects 22 created by implanting hydrogen ion into the second silicon substrate 20. The crystal plane of the second silicon substrate 20 is oriented substantially orthogonal to the crystal plane of the first silicon layer 19. The second silicon substrate 20 is split and removed alonf the line of defects 22 leaving behind the second insulating layer 24 and a second silicon layer 25 on the silicon-on-insulator structure. A plurality of devices with different crystal orientations can be subsequently formed on a single, planar silicon-on-insulator structure by selectively etching the silicon-on-insulator structure down to silicon layers of different crystal orientations, growing selective epitaxial silicon layers in the etched regions, and subsequently planarizing the silicon-on-insulator structure by chemical-mechanical polishing.

公开(公告)号：WO2004105135A1

公开(公告)日：2004-12-02

申请号：PCT/US2004/000764

申请日：2004-01-09

Applicant: ADVANCED MICRO DEVICES, INC. ,  WU, David, Donggang ,  CHEEK, Jon, D.

Inventor： WU, David, Donggang ,  CHEEK, Jon, D.

IPC: H01L27/08

CPC classification number: H01L27/0802

Abstract: A resistive structure (102) formed overlying a semiconductor substrate is masked with a silicide block layer (120) to define a portion of the resistive structure that is to be unsilicided and a portion of the resistive structure to be silicided. The silicide block layer (120) is changed to facilitate different processes.

Abstract translation: 形成在半导体衬底上的电阻结构（102）用硅化物阻挡层（120）掩蔽以限定待被剥离的电阻结构的一部分，并且电阻结构的一部分被硅化。 改变硅化物阻挡层（120）以促进不同的工艺。

公开(公告)号：WO2003054951A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041103

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUNING, Scott ,  KADOSH, Daniel ,  CHEEK, Jon, D. ,  BULLER, James, F.

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/2652

Abstract: A method of forming a semiconductor device provides a gate electrode (32) on a substrate (30); and an oxide liner (34) that is less than 100 A in thickness on the substrate (30) and the gate electrode (32). A nitride layer (38) is formed on the oxide liner (34). The nitride layer (38) is etched to form nitride spacers (40), the etching stopping on the oxide liner (34). The thinner oxide liner (34), e.g., less than 100 A, prevents the liner (34) from acting as a sink for dopants during thermal processing so that the dopants in the source/drain extension regions (36) and the source/drain regions (42) remain in the substrate (30) during the thermal processing, thereby preventing degradation of transistor performance.

Abstract translation: 形成半导体器件的方法在衬底（30）上提供栅电极（32）; 以及在所述基板（30）和所述栅电极（32）上的厚度小于100A的氧化物衬垫（34）。 在氧化物衬垫（34）上形成氮化物层（38）。 蚀刻氮化物层（38）以形成氮化物间隔物（40），蚀刻停止在氧化物衬垫（34）上。 较薄的氧化物衬垫（34）（例如小于100A）可防止衬垫（34）在热处理期间充当掺杂剂的沉陷，使得源极/漏极延伸区域（36）和源极/漏极 在热处理期间，区域（42）保留在基板（30）中，从而防止晶体管性能的劣化。

公开(公告)号：EP1504470A1

公开(公告)日：2005-02-09

申请号：EP02790146.1

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BULLER, James, F. ,  CHEEK, Jon, D.

IPC: H01L21/8234

CPC classification number: H01L21/823462

Abstract: In one illustrative embodiment, the method comprises forming a sacrificial layer of material (34) above a substrate (30) comprised of silicon, performing a wet etching process to remove the sacrificial layer (34), implanting fluorine atoms into selected portions of the substrate (30) after the sacrificial layer (34) is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers (42, 44) above the substrate (30), the gate insulation layers (42) formed above the fluorine implanted selected portions of the substrate (30) having a thickness that is greater than a thickness of the gate insulation layers (44) formed above portions of the substrate (30) not implanted with fluorine.

公开(公告)号：EP1695389A1

公开(公告)日：2006-08-30

申请号：EP04794688.4

申请日：2004-10-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PAN, James, N. ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/78639

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions (15) are provided on a substrate (12) with a gate electrode (16) formed on the uppermost channel region (15), separated by a gate oxide (14c), for example. The vertical stacking of multiple channels (15) and the gate electrode (16) permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.