公开(公告)号：WO1997047115A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001857

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SINGH, Alok ,  ROY, Rajat

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

Abstract translation: 一种精确识别存储器件中包位置结束的方法。 存储器设备中的第一和第二存储器位置被保留，并且在顺序存储器位置中将一系列数据写入存储器件。 当最后一个数据序列被写入存储器时，存储器位置被写入第一保留存储器位置。 第二个内存位置被写入以显示分组的结束已被写入存储器。

公开(公告)号：WO1997046944A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001634

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

Abstract translation: 一个以太网控制器，用于控制站和具有四个FIFO的以太网之间的数据传输，用于管理站CPU，存储器缓冲区和以太网之间的数据传输。 四个FIFO都具有选定的大小以最大化控制器的性能。 控制器包括仲裁器，用于仲裁来自每个FIFO的待决请求将具有优先级。 控制器将每个FIFO的数据传输限制为每个授权32个字节。 每个FIFO包括将第一位大小格式的数据转换为第二位大小格式的逻辑。 控制器还包括将16位地址转换为两个8位部分以用于通过8位地址总线传输的逻辑，以及将两个8位部分重新格式化为16位地址的逻辑。

公开(公告)号：EP0904651B1

公开(公告)日：2003-10-15

申请号：EP97906496.1

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

公开(公告)号：EP0976054B1

公开(公告)日：2001-08-29

申请号：EP97904161.3

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

公开(公告)号：EP0976054A1

公开(公告)日：2000-02-02

申请号：EP97904161.3

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

公开(公告)号：EP0904651A1

公开(公告)日：1999-03-31

申请号：EP97906496.0

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat

IPC: H04L13 ,  H04L29 ,  H04L12

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.