公开(公告)号：WO1997046944A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001634

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

Abstract translation: 一个以太网控制器，用于控制站和具有四个FIFO的以太网之间的数据传输，用于管理站CPU，存储器缓冲区和以太网之间的数据传输。 四个FIFO都具有选定的大小以最大化控制器的性能。 控制器包括仲裁器，用于仲裁来自每个FIFO的待决请求将具有优先级。 控制器将每个FIFO的数据传输限制为每个授权32个字节。 每个FIFO包括将第一位大小格式的数据转换为第二位大小格式的逻辑。 控制器还包括将16位地址转换为两个8位部分以用于通过8位地址总线传输的逻辑，以及将两个8位部分重新格式化为16位地址的逻辑。

公开(公告)号：WO1997047116A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001858

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ROY, Rajat ,  DWORK, Jeffrey ,  FISCHER, Jenny, Liu

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L12/40013 ,  H04L12/413 ,  H04L49/90

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller (14). The data structure includes the data to be transmitted (58, 60, 76, 82), the STATUS information (62, 84) of the data to be transmitted, and the DESCRIPTOR information (64, 86) of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32-bit STATUS information is organized in four 8-bit bytes in a 32-bit row, and the 32-bit DESCRIPTOR information is organized in four 8-bit bytes in a 32-bit row. A one-bit tag field (66, 72) is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

Abstract translation: 一种在以太网控制器（14）的发送部分中提供高性能的数据结构。 数据结构包括待发送的数据（58,60,76,82），要发送的数据的状态信息（62,84）和要发送的数据的DESCRIPTOR信息（64,86）。 数据以32位行的8位字节组织，32位STATUS信息以32位行的四个8位字节组织，32位DESCRIPTOR信息组织在四位8位 32位行中的字节。 一比特标签字段（66,72）与每个行相关联，并且标签字段中的1表示分组结束位于与该标签相关联的行中。 STATUS字节的低4位包含指示该行中哪个字节包含数据包结束的信息。

公开(公告)号：WO1998006197A1

公开(公告)日：1998-02-12

申请号：PCT/US1997003578

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ROY, Rajat ,  KUO, Jerry, Chun-Jen ,  ANNADURAI, Andy, P.

IPC: H04L07/00

CPC classification number: H04L7/0083 ,  G06F1/08

Abstract: A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.

Abstract translation: 用于在不同频率的不同频率时钟域之间切换的电路和方法。 电路具有用于选择要输出哪个频域的选择输入，与第一时钟域相关联的第一电路以及与第二时钟域相关联的第二电路。 第一和第二电路响应于选择输入并一起工作以在第二时钟接合之前解除第一时钟。

公开(公告)号：WO1997047115A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001857

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SINGH, Alok ,  ROY, Rajat

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

Abstract translation: 一种精确识别存储器件中包位置结束的方法。 存储器设备中的第一和第二存储器位置被保留，并且在顺序存储器位置中将一系列数据写入存储器件。 当最后一个数据序列被写入存储器时，存储器位置被写入第一保留存储器位置。 第二个内存位置被写入以显示分组的结束已被写入存储器。

公开(公告)号：EP0903029A1

公开(公告)日：1999-03-24

申请号：EP97905784.0

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ROY, Rajat ,  DWORK, Jeffrey ,  FISCHER, Jenny, Liu

IPC: G06F13 ,  F25J1 ,  F25J3 ,  H04L12 ,  H04L29

CPC classification number: H04L29/06 ,  H04L12/40013 ,  H04L12/413 ,  H04L49/90

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller (14). The data structure includes the data to be transmitted (58, 60, 76, 82), the STATUS information (62, 84) of the data to be transmitted, and the DESCRIPTOR information (64, 86) of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32-bit STATUS information is organized in four 8-bit bytes in a 32-bit row, and the 32-bit DESCRIPTOR information is organized in four 8-bit bytes in a 32-bit row. A one-bit tag field (66, 72) is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

公开(公告)号：EP0904651B1

公开(公告)日：2003-10-15

申请号：EP97906496.1

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

公开(公告)号：EP0903029B1

公开(公告)日：2004-05-19

申请号：EP97905784.1

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ROY, Rajat ,  DWORK, Jeffrey ,  FISCHER, Jenny, Liu

IPC: H04L29/06 ,  H04L12/413

CPC classification number: H04L29/06 ,  H04L12/40013 ,  H04L12/413 ,  H04L49/90

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller (14). The data structure includes the data to be transmitted (58, 60, 76, 82), the STATUS information (62, 84) of the data to be transmitted, and the DESCRIPTOR information (64, 86) of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32-bit STATUS information is organized in four 8-bit bytes in a 32-bit row, and the 32-bit DESCRIPTOR information is organized in four 8-bit bytes in a 32-bit row. A one-bit tag field (66, 72) is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

公开(公告)号：EP0976054B1

公开(公告)日：2001-08-29

申请号：EP97904161.3

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

公开(公告)号：EP0976054A1

公开(公告)日：2000-02-02

申请号：EP97904161.3

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

公开(公告)号：EP0904651A1

公开(公告)日：1999-03-31

申请号：EP97906496.0

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Alok ,  ROY, Rajat

IPC: H04L13 ,  H04L29 ,  H04L12

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.