公开(公告)号：JPH04227531A

公开(公告)日：1992-08-17

申请号：JP6645491

申请日：1991-03-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO EMU PAARUMAN ,  BURAIAN DEI MATSUKUMIN ,  GUREN EI TAMURA ,  RAYU BESUJIESUNA ,  PUREMU SOOBERU ,  ROBAATO SHII SEIDEN ,  TOOMASU DABURIYU RINCHI

IPC: G06F7/00 ,  G06F7/38 ,  G06F7/483 ,  G06F7/527 ,  G06F7/53 ,  G06F7/57 ,  G06F7/76 ,  G06F9/38

Abstract: PURPOSE: To provide a floating point processor for pipeline-processing a series of calculation of a simple and compound arithmetic operation. CONSTITUTION: At least one arithmetic unit for executing arithmetic operation to an input operand given to the arithmetic unit, at least one accumulator for storing the result of the arithmetic operation executed by the arithmetic unit and a means for giving the result stored in the accumulator to the arithmetic unit are provided. The arithmetic operation is pipeline-processed by a stage deciding means for ordering the input operand, a result calculated by the arithmetic unit by using the input operand and a result calculated by the arithmetic unit by using the input operand and the accumulated operand through the floating point processor.

公开(公告)号：JPH08254571A

公开(公告)日：1996-10-01

申请号：JP26684995

申请日：1995-10-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURAIAN DEI MATSUKUMIN ,  GOPI GANAPASHII

IPC: G01R31/28 ,  G06F17/50 ,  H03K3/037 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To make it possible to emulate a level detecting latch effectively by suing a high-frequency enabled signal, and clocking an edge detecting latch. SOLUTION: A level-detecting emulating circuit 20 has an edge detecting latch 22 and an AND gate 24. The gate 24 receives a system clock signal (PHI) and a high-frequency clock signal (HCLK) and imparts a high-frequency enabled clock signal (HEN) to the latch 22. The latch 22 is a DFF and feeds the signal, which is applied to the D input terminal, to the Q output terminal when a rising edge is fed to the input of the FF. Thus, the edged detecting latch 22 can emulate the level detecting latch. At this time, the frequency ratio of HCLK and PHI is made to be 10:1, and the errors caused by the too low ratio and the waste of the using time caused by the too high ratio are reduced.

公开(公告)号：JPH04227530A

公开(公告)日：1992-08-17

申请号：JP6861591

申请日：1991-04-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUMEETA GUPUTA ,  TOOMASU DABURIYU RINCHI ,  ROBAATO EMU PAARUMAN ,  BURAIAN DEI MATSUKUMIN

IPC: G06F7/00 ,  G06F7/485 ,  G06F7/53 ,  G06F7/57 ,  G06F7/76 ,  G06F9/38

Abstract: PURPOSE: To provide a floating point processing unit making normalization- released input operands which have been given to a multiplication or division unit face the addition/division unit for normalization. CONSTITUTION: A first arithmetic operation unit having a pair of inputs for receiving the first and second operands and output for transmitting the result of an arithmetic operation and a second arithmetic operation unit having the pairs of inputs and outputs are contained. The second arithmetic operation unit includes a normalization releasing unit for releasing the normalization of a normalized number and a normalizing unit for normalizing the number whose normalization is released. The first and second operands are given to the second arithmetic operation unit in which the operand whose normalization is released can be normalized again. The operand which is normalized by the second arithmetic operation unit is given to the first arithmetic operation unit where the arithmetic operation is to be realized.