公开(公告)号：KR20200139812A

公开(公告)日：2020-12-14

申请号：KR20207032316

申请日：2019-04-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SMITH ALAN DODSON ,  KALYANASUNDHARAM VYDHYANATHAN ,  BROUSSARD BRYAN P ,  DONLEY GREGGORY D ,  PATEL CHINTAN S

IPC: H04L12/877 ,  H04L12/841 ,  H04L12/861 ,  H04L12/863 ,  H04L12/873 ,  H04L12/875 ,  H04L12/879

Abstract: 컴퓨팅시스템은데이터를저장하기위한메모리, 네트워크트래픽을생성하기위한하나이상의클라이언트들및 네트워크스위치들과의통신패브릭을사용한다. 네트워크스위치들은별개의입력및 출력저장구조들보다는, 집중화된저장구조들을포함한다. 네트워크스위치들은패킷들의에이지가큐 엔트리위치에대응하는단일의, 집중화된접이형큐에수신된패킷들에대응하는특정한메타데이터를저장한다. 패킷들의페이로드데이터는별개의메모리에저장되며, 따라서비교적많은양의데이터가네트워크스위치에서패킷의수명동안시프트되지않는다. 네트워크스위치들은접이식큐에서희소큐 엔트리들을선택하고, 선택된큐 엔트리들을할당해제하며, 네트워크스위치들의기수에비례하는지연을갖고큐의제 1 단부를향해남아있는할당된큐 엔트리들을시프트시킨다.

公开(公告)号：GB2457618A

公开(公告)日：2009-08-26

申请号：GB0910329

申请日：2007-12-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HUGHES WILLIAM A ,  YANG CHEN-PING ,  DONLEY GREGGORY D ,  FERTIG MICHAEL K

IPC: H04L1/00 ,  G06F11/00 ,  H04L1/18

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >= 2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit, hi another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

公开(公告)号：DE112007003086T5

公开(公告)日：2009-10-08

申请号：DE112007003086

申请日：2007-12-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HUGHES WILLIAM A ,  YANG CHEN-PING ,  DONLEY GREGGORY D ,  FERTIG MICHAEL K

IPC: G06F11/00

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.