公开(公告)号：GB2457618A

公开(公告)日：2009-08-26

申请号：GB0910329

申请日：2007-12-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HUGHES WILLIAM A ,  YANG CHEN-PING ,  DONLEY GREGGORY D ,  FERTIG MICHAEL K

IPC: H04L1/00 ,  G06F11/00 ,  H04L1/18

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >= 2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit, hi another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

公开(公告)号：DE112007003086T5

公开(公告)日：2009-10-08

申请号：DE112007003086

申请日：2007-12-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HUGHES WILLIAM A ,  YANG CHEN-PING ,  DONLEY GREGGORY D ,  FERTIG MICHAEL K

IPC: G06F11/00

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.