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公开(公告)号：DE10394081B4
公开(公告)日：2013-05-29
申请号：DE10394081
申请日：2003-12-22
Applicant: ADVANCED MICRO DEVICES INC
Inventor： HUGHES WILLIAM A , CONWAY PATRICK
IPC: G06F12/08
Abstract: Ein Datenverarbeitungssystem (100, 600) besitzt eine Speicherhierarchie mit einem Pufferspeicher (124, 624) und einem niedriger rangigen Speichersystem (170, 650). Ein Datenelement mit einem speziellen „Schreiben mit Einprägen”-Attribut wird von einem Datenerzeuger (160, 640) empfangen, etwa einer Ethernet-Steuerung. Das Datenelement wird zu dem Pufferspeicher (124, 624) weitergeleitet, ohne auf das niedriger rangige Speichersystem 170, 650) zuzugreifen. Nachfolgend wird mindestens eine Pufferspeicherzeile, die das Datenelement enthält, in dem Pufferspeicher (124, 624) aktualisiert.
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公开(公告)号：DE112006003628T5
公开(公告)日：2008-11-13
申请号：DE112006003628
申请日：2006-12-08
Applicant: ADVANCED MICRO DEVICES INC
Inventor： WHITE SCOTT A , HUGHES WILLIAM A , MADRID PHILLIP E
Abstract: Multiple logic cores of integrated circuits and processors may be configured to operate at frequencies and voltages independently of each other. Additionally, other components, such as a common bridge configured to interface with the logic cores, may operate at a voltage and frequency independent of the voltage and frequency at which the logic cores are operating. The operating frequency and/or voltage of a logic core may be independently adjusted for various reasons, including power management and temperature control. Logic circuitry at an interface between the controller and the logic cores may translate logic signals from one voltage and/or frequency to another to enable communication between the bridge and the logic core when the two are operating at different voltages and/or frequencies.
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公开(公告)号：GB2447392A
公开(公告)日：2008-09-10
申请号：GB0812573
申请日：2008-07-10
Applicant: ADVANCED MICRO DEVICES INC
Inventor： WHITE SCOTT A , HUGHES WILLIAM A , MADRID PHILIP E
Abstract: Multiple logic cores (120) of integrated circuits and processors may be configured to operate at frequencies and voltages independently of each other. Additionally, other components, such as a common bridge (110) configured to interface with the logic cores, may operate at a voltage and frequency independent of the voltage and frequency at which the logic cores are operating. The operating frequency and/or voltage of a logic core may be independently adjusted for various reasons, including power management and temperature control. Logic circuitry at an interface between the controller and the logic cores may translate logic signals from one voltage and/or frequency to another to enable communication between the bridge and the logic core when the two are operating at different voltages and/or frequencies.
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公开(公告)号：DE112004001605T5
公开(公告)日：2006-07-06
申请号：DE112004001605
申请日：2004-06-04
Applicant: ADVANCED MICRO DEVICES INC
Inventor： GULICK DALE E , STRONGIN GEOFFREY S , HUGHES WILLIAM A
Abstract: A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory configured to store data in a plurality of locations. The computer system also includes a memory controller which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.
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公开(公告)号：GB2447392B
公开(公告)日：2009-12-16
申请号：GB0812573
申请日：2008-07-10
Applicant: ADVANCED MICRO DEVICES INC
Inventor： WHITE SCOTT A , HUGHES WILLIAM A , MADRID PHILIP E
Abstract: Multiple logic cores of integrated circuits and processors may be configured to operate at frequencies and voltages independently of each other. Additionally, other components, such as a common bridge configured to interface with the logic cores, may operate at a voltage and frequency independent of the voltage and frequency at which the logic cores are operating. The operating frequency and/or voltage of a logic core may be independently adjusted for various reasons, including power management and temperature control. Logic circuitry at an interface between the controller and the logic cores may translate logic signals from one voltage and/or frequency to another to enable communication between the bridge and the logic core when the two are operating at different voltages and/or frequencies.
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Patent Agency Ranking
公开(公告)号：GB2457618A
公开(公告)日：2009-08-26
申请号：GB0910329
申请日：2007-12-13
Applicant: ADVANCED MICRO DEVICES INC
Inventor： HUGHES WILLIAM A , YANG CHEN-PING , DONLEY GREGGORY D , FERTIG MICHAEL K
Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >= 2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit, hi another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
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公开(公告)号：GB2413879B
公开(公告)日：2006-08-16
申请号：GB0516391
申请日：2003-12-22
Applicant: ADVANCED MICRO DEVICES INC
Inventor： HUGHES WILLIAM A , CONWAY PATRICK
IPC: G06F12/08
Abstract: A data processing system ( 100, 600 ) has a memory hierarchy including a cache ( 124, 624 ) and a lower-level memory system ( 170, 650 ). A data element having a special write with inject attribute is received from a data producer ( 160, 640 ), such as an Ethernet controller. The data element is forwarded to the cache ( 124, 624 ) without accessing the lower-level memory system ( 170, 650 ). Subsequently at least one cache line containing the data element is updated in the cache ( 124, 624 ).
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公开(公告)号：GB2422228A
公开(公告)日：2006-07-19
申请号：GB0604581
申请日：2004-06-04
Applicant: ADVANCED MICRO DEVICES INC
Inventor： GULICK DALE E , STRONGIN GEOFFREY S , HUGHES WILLIAM A
Abstract: A computer system (10) includes a processor (IOOA) which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory (11 OA) configured to store data in a plurality of locations. The computer system also includes a memory controller (101A) which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.
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公开(公告)号：DE10394081T5
公开(公告)日：2011-12-29
申请号：DE10394081
申请日：2003-12-22
Applicant: ADVANCED MICRO DEVICES INC
Inventor： HUGHES WILLIAM A , CONWAY PATRICK
IPC: G06F12/08
Abstract: Ein Datenverarbeitungssystem (100, 600) besitzt eine Speicherhierarchie mit einem Pufferspeicher (124, 624) und einem niedriger rangigen Speichersystem (170, 650). Ein Datenelement mit einem speziellen „Schreiben mit Einprägen”-Attribut wird von einem Datenerzeuger (160, 640) empfangen, etwa einer Ethernet-Steuerung. Das Datenelement wird zu dem Pufferspeicher (124, 624) weitergeleitet, ohne auf das niedriger rangige Speichersystem 170, 650) zuzugreifen. Nachfolgend wird mindestens eine Pufferspeicherzeile, die das Datenelement enthält, in dem Pufferspeicher (124, 624) aktualisiert.
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公开(公告)号：DE112007003086T5
公开(公告)日：2009-10-08
申请号：DE112007003086
申请日：2007-12-13
Applicant: ADVANCED MICRO DEVICES INC
Inventor： HUGHES WILLIAM A , YANG CHEN-PING , DONLEY GREGGORY D , FERTIG MICHAEL K
IPC: G06F11/00
Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
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