公开(公告)号：JPH04227536A

公开(公告)日：1992-08-17

申请号：JP6841491

申请日：1991-04-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SARIMU EI SHIYAA ,  TOOMASU DABURIYU RINCHI

IPC: G06F7/50 ,  G06F7/509 ,  G06F7/52 ,  G06F7/535

Abstract: PURPOSE: To provide a digital divider which uses a single compact conservation adder to reduce the iterative delay of an addition operation, to increase the dividing speed and to reduce the hardware scale. CONSTITUTION: The divider is composed of a quotient prediction logic block 4 and a special carry conservation adder 20. The adder 20 attains a multiplexer function and three operand additions via a single adder. In such a constitution, the iterative delay equals to the total delay of the adder 20 and the block 4. The delay of the adder 20 is smaller than the delay of a single gate, so that the total delay time can be reduced.

公开(公告)号：JPH06222994A

公开(公告)日：1994-08-12

申请号：JP31773093

申请日：1993-12-17

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SARIMU EI SHIYAA

IPC: G06F12/08

Abstract: PURPOSE: To allow a multicache memory to operate together by allowing a cache connected with a certain CPU to recognize a memory request from another CPU, to judge whether or not this includes requested data, and to transmit the requested data to a proper cache. CONSTITUTION: In a multiprocessing system equipped with a shared main memory 1, a cache memory is useful not only for increasing the speed of memory access, but also for reducing a competition level on a main memory bus 4 for access to the main memory 1. When a CPU 2 requests effective data only in a cache 5 from a cache 3, the cache 5 including data requested by the CPU 2 recognizes the request, judges whether or not the cache 5 has the requested data, and transmits the data to the cache 3 for using the data.

公开(公告)号：JPH06222993A

公开(公告)日：1994-08-12

申请号：JP31006093

申请日：1993-12-10

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SARIMU EI SHIYAA

IPC: G06F12/08

Abstract: PURPOSE: To provide a method for supplying information to a processor in a multiple cache by screening a memory access, and freeing a cache, and to provide a circuit for realizing this method. CONSTITUTION: A cache control circuit reduces access to a main memory 20 in a multiple cache multiple processing system. Plural caches 12-15 can be used with one central processing unit 10, and a burst mode operation can be simplified by this circuit.

公开(公告)号：JPH04227535A

公开(公告)日：1992-08-17

申请号：JP6841391

申请日：1991-04-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU DABURIYU RINCHI ,  KEN CHIEN ,  TONII HAASON ,  SUTEIIBUN DEII MAKINTAIA ,  SARIMU EI SHIYAA

IPC: G06F7/483 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552

Abstract: PURPOSE: To provide a fast divider which minimizes the volume of a logic circuit while increasing the dividing speed and also performs the separate iterative division with a radix 4 and the square root calculation with a radix 2 respectively. CONSTITUTION: A bus A is connected to a 1st quotient predictor 102 and a partial remainder register 106, and a bus B is connected to the predictor 102, a shifter 103, the 1st input of an adder 104, and a division register 108. The dividend, divisor and quotient are outputted by a divider 100 through the bus A, the bus B and a result bus respectively. The divider 100 is controlled by a divider controller 110. The controller 110 receives an instruction via a bus I and produces the control signals of division operations for the predictor 102, the register 106, the register 108, a 1st quotient register 114a, a 2nd quotient register 114b, a 3X divisor register 116, a zero detection means 122 and a remainder code detection means 123.