公开(公告)号：JPH0773019A

公开(公告)日：1995-03-17

申请号：JP6339191

申请日：1991-03-27

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU DABURIYU RINCHI ,  SUTEIIBUN DEII MAKINTAIA

IPC: G06F7/483 ,  G06F7/49 ,  G06F7/50 ,  G06F7/507 ,  G06F7/508 ,  G06F7/527

Abstract: PURPOSE: To obtain a speedy and relatively small high base carry look ahead tree by allowing each of plural tree nodes to include a carry chain or the deformation, and/or an HAND gate chain or the deformation. CONSTITUTION: Three different types of blocks are arrayed in three levels. The first level includes 15 corrected carry chain blocks 74-102, and a carry chain block 104 corrected for carry-in, and block propagation and generation is generated for four input positions. The second level includes four Manchester carry chain nodes 106-112, and the block propagation and generation is generated from the four of the first level. Therefore, the second level provides information related with 4×4 or 16 bit blocks. The third level includes two Manchester carry chain nodes 114 and 116, and provides block information related with the four or 4×(4×4) or 64 hits of the blocks of the second level.

公开(公告)号：JPH04227535A

公开(公告)日：1992-08-17

申请号：JP6841391

申请日：1991-04-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU DABURIYU RINCHI ,  KEN CHIEN ,  TONII HAASON ,  SUTEIIBUN DEII MAKINTAIA ,  SARIMU EI SHIYAA

IPC: G06F7/483 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552

Abstract: PURPOSE: To provide a fast divider which minimizes the volume of a logic circuit while increasing the dividing speed and also performs the separate iterative division with a radix 4 and the square root calculation with a radix 2 respectively. CONSTITUTION: A bus A is connected to a 1st quotient predictor 102 and a partial remainder register 106, and a bus B is connected to the predictor 102, a shifter 103, the 1st input of an adder 104, and a division register 108. The dividend, divisor and quotient are outputted by a divider 100 through the bus A, the bus B and a result bus respectively. The divider 100 is controlled by a divider controller 110. The controller 110 receives an instruction via a bus I and produces the control signals of division operations for the predictor 102, the register 106, the register 108, a 1st quotient register 114a, a 2nd quotient register 114b, a 3X divisor register 116, a zero detection means 122 and a remainder code detection means 123.

公开(公告)号：JPH04227533A

公开(公告)日：1992-08-17

申请号：JP6849891

申请日：1991-04-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU DABURIYU RINCHI ,  SUTEIIBUN DEII MAKINTAIA

IPC: G06F7/507 ,  G06F7/49 ,  G06F7/50 ,  G06F7/508 ,  G06F9/305

Abstract: PURPOSE: To provide a high speed adder with less delay due to carry generation. CONSTITUTION: This high speed adder is fit to be incorporated into an electronic digital processing circuit. At least one first independent adder assuming the carry-in of zero (0), at least one second independent adder assuming the carry-in of one (1), a means for generating a carry to the first and second independent adders which can simultaneously be operated and a final multiplexer for generating a precise result based on output received from the first and second independent adders and the means for generating the carry.