公开(公告)号：JPH04227535A

公开(公告)日：1992-08-17

申请号：JP6841391

申请日：1991-04-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU DABURIYU RINCHI ,  KEN CHIEN ,  TONII HAASON ,  SUTEIIBUN DEII MAKINTAIA ,  SARIMU EI SHIYAA

IPC: G06F7/483 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552

Abstract: PURPOSE: To provide a fast divider which minimizes the volume of a logic circuit while increasing the dividing speed and also performs the separate iterative division with a radix 4 and the square root calculation with a radix 2 respectively. CONSTITUTION: A bus A is connected to a 1st quotient predictor 102 and a partial remainder register 106, and a bus B is connected to the predictor 102, a shifter 103, the 1st input of an adder 104, and a division register 108. The dividend, divisor and quotient are outputted by a divider 100 through the bus A, the bus B and a result bus respectively. The divider 100 is controlled by a divider controller 110. The controller 110 receives an instruction via a bus I and produces the control signals of division operations for the predictor 102, the register 106, the register 108, a 1st quotient register 114a, a 2nd quotient register 114b, a 3X divisor register 116, a zero detection means 122 and a remainder code detection means 123.