公开(公告)号：JPH0715291A

公开(公告)日：1995-01-17

申请号：JP233194

申请日：1994-01-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TAN TORAN ,  GOPI GANAPASHII ,  MAIKERU DEI GOTSUDAADO ,  ROBAATO SATSUDEN

IPC: H03K3/356 ,  G06F13/40

Abstract: PURPOSE: To remove precharge rippling, and to remove a noise by providing a latch circuit for delaying the latching of data from a bus to a receiving circuit. CONSTITUTION: Data from a pre-charged data bus are transmitted to a data line 4, and the input of a latch 20 is connected with the data line 4, and the output of the latch 20 is connected with the receiving circuit of an asynchronizing circuit 22. The gate of the latch 20 is connected with the output of a structure for activating latch, and a pre-charge value is not transmitted from the pre-charged bus to the asynchronizing circuit 22. The activating structure includes an AND gate 32, and this is provided with input lines 34 and 36 and an output. At that time, inverted DATA VALID signal and DATA CLOCK signal are received by the AND gate 32, and the output is turned into an H level only when the pre-charged bus is operated with a data drive phase, and the data are driven by the precharged bus. Therefore, the latch 20 is not activated until the data are driven by the precharged bus.

公开(公告)号：JPH06243039A

公开(公告)日：1994-09-02

申请号：JP233094

申请日：1994-01-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TAN TORAN

IPC: G06F9/38 ,  G06F12/08

Abstract: PURPOSE: To allow an instruction buffer to efficiently write data in a cache. CONSTITUTION: This cache memory system is constituted of the combination of an instruction cache and a prefetch buffer 36. Thus, any necessity for a bus mutually connecting the cache with the buffer can be canceled, the validity of the a perfected instruction can be improved, the usage of a power and a silicon space can be reduced, and data can be efficiently written in the cache by an instruction buffer.

公开(公告)号：JPH06282983A

公开(公告)日：1994-10-07

申请号：JP233394

申请日：1994-01-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UIRIAMU MAIKERU JIYONSON ,  TAN TORAN ,  SUTEIIBUN CHIYAARUZU KUROMAA

IPC: G06F12/02 ,  G11C7/10 ,  G11C11/401

Abstract: PURPOSE: To improve the performance of DRAM access by performing DRAM page mode access for one cycle at high operating frequency corresponding to a column address strobe(CAS) signal. CONSTITUTION: Both a low CAS time and usable CAS access time is 0.4fold as long as lock cycle time and respective data bytes can be latched by the rising edges of respective CAS. Thus, distortion between the falling edge of CAS and the rising edge of a clock as the factors of usable access time is removed and the CAS signal can latch data. Besides, the page mode access is utilized for reloading a data cache block. Thus, the method for high- performance DRAM access can be provided.

公开(公告)号：JPH06282489A

公开(公告)日：1994-10-07

申请号：JP233294

申请日：1994-01-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UIRIAMU MAIKERU JIYONSON ,  TAN TORAN

IPC: G06F12/08 ,  G06F12/0855

Abstract: PURPOSE: To freely process a next load request from an execution unit that a cache corresponds to by writing reloaded data in a buffer before the data is written in the cache. CONSTITUTION: A block size buffer 26 is arranged between a main memory 14 and the data cache 18. If a cache miss is made, the cache 18 begins to be reloaded from the main memory 14 and data reloaded into the cache 18 from the main memory 14 in the next stage is moved to the buffer 26 and sent to a processor 18 to comply with a 1st request. The cache 18 can process a next load request 20 from the processor 12. Here, when caching is hit, the data is sent from the cache 18 to an execution unit in the next stage. If a cache miss is made as to the next request 20, the cache is only accessed again after reloading is completed through the buffer 26.