公开(公告)号：WO2004040623A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/035433

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RUELKE, Hartmut ,  HOHAGE, Joerg ,  WERNER, Thomas ,  AMINPUR, Massud

IPC: H01L21/00

CPC classification number: H01L21/76834 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76822 ,  H01L21/76826

Abstract: The effect of resist poisoning may be eliminated or at least substantially reduced in the formation of a low-k metallization layer, in that a nitrogen-containing barrier/etch stop layer (250) is provided with a significantly reduced nitrogen concentration at an interface (251) in contact with said low-k dielectric material 206. Consequently, diffusion of nitrogen and nitrogen compounds in vias formed in said low-k dielectric layer (206) is significantly suppressed, so that in a subsequent photolithographic step, interaction of nitrogen and nitrogen compounds with the photoresist is remarkably reduced.

Abstract translation: 在形成低k金属化层时，抗蚀剂中毒的效果可以被消除或者至少基本上减少，因为含氮阻挡/蚀刻停止层（250）设置有 显着降低与所述低k电介质材料206接触的界面（251）处的氮浓度。因此，氮和氮化合物在所述低k电介质层（206）中形成的过孔中的扩散被显着抑制，使得在 随后的光刻步骤中，氮和氮化合物与光致抗蚀剂的相互作用显着降低。

公开(公告)号：WO2005119760A1

公开(公告)日：2005-12-15

申请号：PCT/US2005/010516

申请日：2005-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  FROHBERG, Kai ,  SCHALLER, Matthias ,  AMINPUR, Massud

Inventor： FROHBERG, Kai ,  SCHALLER, Matthias ,  AMINPUR, Massud

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823412 ,  H01L29/7842 ,  H01L29/7843

Abstract: By providing a contact etch stop layer (116), the stress in channel regions of different transistor types (100N), (100P) may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer (116) may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor (100N), (100P) performance may be obtained while not significantly contributing to process complexity.

Abstract translation: 通过提供接触蚀刻停止层（116），可以有效地控制不同晶体管类型（100N），（100P）的沟道区域中的应力，其中可以获得接触蚀刻停止层（116）的拉伸和压缩应力部分 通过熟知的工艺，例如湿化学蚀刻，等离子体蚀刻，离子注入，等离子体处理等。 因此，可以获得晶体管（100N），（100P）性能的显着改善，而不显着地促进工艺复杂性。

公开(公告)号：WO2004021430A1

公开(公告)日：2004-03-11

申请号：PCT/US2003/022695

申请日：2003-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HELLIG, Kay ,  AMINPUR, Massud

IPC: H01L21/66

CPC classification number: H01L21/31116

Abstract: A method is presented to increase, by means of dummy via or contact structures, the open areas to 5 % or more of the total wafer area in a semiconductor manufacturing process, e.g., contact/via etch processes for interconnect layers. An open area of 5 % or more allows robust endpoint detection using optical emission from the plasma, or electrical signals from the RF system. An end-pointed via/contact etch process overcomes the problems encountered due to the effects of aspect-ratio dependent etching, etch rate differences between tools, etch rate fluctuations over time, and deviations of mean incoming film thickness. With end-pointed etching, only the sources of non-uniformity over the wafer have to be considered during etch, which reduces the amount of over-etch built into a conventional via/contact etch process. The dummy structures may be redundant (functional) structures or "true" dummy (non-functional) structures. The dummy structures have the same size as functional structures.

Abstract translation: 提出了一种通过虚拟通孔或接触结构将开放区域增加到半导体制造工艺中的总晶片面积的5％或更多的方法，例如用于互连层的接触/通孔蚀刻工艺的方法。 5％以上的开放区域允许使用来自等离子体的光发射或来自RF系统的电信号进行鲁棒的端点检测。 端点通孔/接触蚀刻工艺克服了由于长宽比依赖蚀刻，工具之间的蚀刻速率差异，时间上的蚀刻速率波动和平均进入膜厚度的偏差的影响而遇到的问题。 通过尖端蚀刻，在蚀刻期间只需要考虑晶片上的不均匀性源，这减少了内置到常规通孔/接触蚀刻工艺中的过度蚀刻的量。 虚拟结构可以是冗余（功能）结构或“真实”虚拟（非功能）结构。 虚拟结构具有与功能结构相同的尺寸。

公开(公告)号：WO2005013357A1

公开(公告)日：2005-02-10

申请号：PCT/US2003/041684

申请日：2003-12-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HELLIG, Kay ,  AMINPUR, Massud

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  G11C8/08 ,  H01L21/743 ,  H01L21/84 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method [600] for forming an integrated circuit includes etching a first opening [228] [338] [402] to a first depth in a dielectric material [322] over a semiconductor device [317] on a first semiconductor substrate [202] and etching a second opening [230] [340] [404] to a second depth in the dielectric material [322] over the first semiconductor substrate [202]. The first and second openings [228] [338] [402] [230] [340] [404] are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings [228] [338] [402] [230] [340] [404] are filled with conductive material.

Abstract translation: 用于形成集成电路的方法[600]包括在第一半导体衬底[202]上的半导体器件[317]上蚀刻第一开口[338] [402]至电介质材料[322]中的第一深度， 并且将第二开口[230] [340] [404]蚀刻到第一半导体衬底[202]上的介电材料[322]中的第二深度。 由于蚀刻滞后，第一和第二开口的大小不同，以大致相同的时间分别蚀刻到第一和第二深度。 第一和第二开口[228] [402] [230] [340] [404]填充有导电材料。

公开(公告)号：WO2003103057A1

公开(公告)日：2003-12-11

申请号：PCT/US2002/041657

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ZISTL, Christian ,  GROSCHOPF, Johannes ,  AMINPUR, Massud

IPC: H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76254 ,  H01L29/78603

Abstract: An SOI substrate includes a diffusion barrier layer (111), the layer thickness and composition of which is selected so as to substantially prevent copper atoms and ions from diffusing through the diffusion barrier layer (111). The diffusion barrier layer (111) is located to substantially reduce the deleterious effect of copper that may be introduced into a semiconductor device from the back side of the substrate (110) during various manufacturing stages of the semiconductor device. In one particular example, a silicon wafer with a silicon nitride layer as a diffusion barrier layer (111) and a silicon wafer with an oxide layer is bonded. After separation, an SOI substrate is obtained that has superior characteristics with respect to resistance against copper back side diffusion.

Abstract translation: SOI衬底包括扩散阻挡层（111），其厚度和组成被选择为基本上防止铜原子和离子扩散通过扩散阻挡层（111）。 定位扩散阻挡层（111），以在半导体器件的各种制造阶段中从衬底（110）的背面大大减少可能被引入半导体器件的铜的有害影响。 在一个具体实例中，结合具有氮化硅层作为扩散阻挡层（111）的硅晶片和具有氧化物层的硅晶片。 分离后，得到相对于铜背面扩散电阻具有优异特性的SOI衬底。

公开(公告)号：EP1330838B1

公开(公告)日：2010-12-01

申请号：EP01957270.0

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AMINPUR, Massud ,  WU, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer (510) above a substrate layer ((505), forming a gate conductor layer (515) above the gate dielectric layer (510), forming a first hard mask layer (540). The method also includes forming a trimmed photoresist mark (570) above the second hard mask layer (550), and forming a patterned hard mask (650) in the second hard mask layer (550) using the trimmed photoresist mask (570) to remove portions (655) of the second hard mask layer (550), the patterned hard mask (650) having a first dimension (δtrim). The method further includes forming a selectively etched hard mask (740) in the first hard mask layer (540) by removing portions (745) of the first hard mask layer (540) adjacent the patterned hard mask (650), the selectively etched hard mask (740) having a second dimension (Δ) less than the first dimension (δtrim), and forming a structure (800) using the selectively etched hard mask (740) to remove portions of the gate conductor layer (515) above the gate dielectric layer (510).

公开(公告)号：EP1330838A1

公开(公告)日：2003-07-30

申请号：EP01957270.0

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AMINPUR, Massud ,  WU, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer (510) above a substrate layer ((505), forming a gate conductor layer (515) above the gate dielectric layer (510), forming a first hard mask layer (540). The method also includes forming a trimmed photoresist mark (570) above the second hard mask layer (550), and forming a patterned hard mask (650) in the second hard mask layer (550) using the trimmed photoresist mask (570) to remove portions (655) of the second hard mask layer (550), the patterned hard mask (650) having a first dimension (δtrim). The method further includes forming a selectively etched hard mask (740) in the first hard mask layer (540) by removing portions (745) of the first hard mask layer (540) adjacent the patterned hard mask (650), the selectively etched hard mask (740) having a second dimension (Δ) less than the first dimension (δtrim), and forming a structure (800) using the selectively etched hard mask (740) to remove portions of the gate conductor layer (515) above the gate dielectric layer (510).