公开(公告)号：WO2008042140A1

公开(公告)日：2008-04-10

申请号：PCT/US2007/020588

申请日：2007-09-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  WAITE, Andrew, M. ,  LUNING, Scott

Inventor： WAITE, Andrew, M. ,  LUNING, Scott

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A stressed field effect transistor (40) and methods for its fabrication are provided. The field effect transistor (40) comprises a silicon substrate (44) with a gate insulator (54) overlying the silicon substrate. A gate electrode (62) overlies the gate insulator and defines a channel region (68) in the silicon substrate underlying the gate electrode. A first silicon germanium region (76) having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region (82) having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract translation: 提供了一种应力场效应晶体管（40）及其制造方法。 场效应晶体管（40）包括硅衬底（44），其上覆盖硅衬底上的栅极绝缘体（54）。 栅电极（62）覆盖栅极绝缘体并且在栅电极下面的硅衬底中限定沟道区（68）。 具有第一厚度的第一硅锗区域（76）嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区隔开的第二厚度的第二硅锗区域（82）也嵌入在硅衬底中。

公开(公告)号：WO2003054951A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041103

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUNING, Scott ,  KADOSH, Daniel ,  CHEEK, Jon, D. ,  BULLER, James, F.

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/2652

Abstract: A method of forming a semiconductor device provides a gate electrode (32) on a substrate (30); and an oxide liner (34) that is less than 100 A in thickness on the substrate (30) and the gate electrode (32). A nitride layer (38) is formed on the oxide liner (34). The nitride layer (38) is etched to form nitride spacers (40), the etching stopping on the oxide liner (34). The thinner oxide liner (34), e.g., less than 100 A, prevents the liner (34) from acting as a sink for dopants during thermal processing so that the dopants in the source/drain extension regions (36) and the source/drain regions (42) remain in the substrate (30) during the thermal processing, thereby preventing degradation of transistor performance.

Abstract translation: 形成半导体器件的方法在衬底（30）上提供栅电极（32）; 以及在所述基板（30）和所述栅电极（32）上的厚度小于100A的氧化物衬垫（34）。 在氧化物衬垫（34）上形成氮化物层（38）。 蚀刻氮化物层（38）以形成氮化物间隔物（40），蚀刻停止在氧化物衬垫（34）上。 较薄的氧化物衬垫（34）（例如小于100A）可防止衬垫（34）在热处理期间充当掺杂剂的沉陷，使得源极/漏极延伸区域（36）和源极/漏极 在热处理期间，区域（42）保留在基板（30）中，从而防止晶体管性能的劣化。

公开(公告)号：WO2003054952A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041331

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物（40）下形成复合氧化物/氮化物衬垫（24,25）来制造。 实例包括通过解耦等离子体沉积沉积保形氧化物层（24），通过解耦等离子体沉积沉积共形氮化物层（25），沉积间隔层（30）然后蚀刻。

公开(公告)号：WO1998008252A1

公开(公告)日：1998-02-26

申请号：PCT/US1997014881

申请日：1997-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LUNING, Scott ,  KUAN-YU LIU, David

IPC: H01L21/762

CPC classification number: H01L21/76221 ,  H01L21/32

Abstract: A local oxidation of silicon (LOCOS) process directed to forming differential field oxide thickness on a single wafer in one patterning step and one growth step. When patterning the masking layer, at least two window widths are formed in the masking layer, exposing the underlying substrate and pad oxide. When one of the window widths is sufficiently small, oxidation of the substrate will be inhibited causing reduced growth and thus a reduced field oxide thickness in that window as compared to other larger windows formed in the same masking layer, creating differential field oxide thicknesses in one growth step.

Abstract translation: 在一个图案化步骤和一个生长步骤中，局部氧化硅（LOCOS）工艺旨在在单个晶片上形成差分场氧化物厚度。 当图案化掩模层时，在掩模层中形成至少两个窗口宽度，暴露下面的衬底和衬垫氧化物。 当窗口宽度之一足够小时，与在相同掩模层中形成的其它较大的窗口相比，衬底的氧化将被抑制，导致生长减小并且因此减小了该窗口中的场氧化物厚度，从而在一个窗口中产生差异的场氧化物厚度 成长步骤

公开(公告)号：WO2005045924A1

公开(公告)日：2005-05-19

申请号：PCT/US2004/031038

申请日：2004-09-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  VAN BENTUM, Ralf ,  LUNING, Scott ,  KAMMLER, Thorsten

Inventor： VAN BENTUM, Ralf ,  LUNING, Scott ,  KAMMLER, Thorsten

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L29/665 ,  H01L29/66628

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract translation: 可以对于不同的器件区域单独地调整极限比例的半导体器件中的外延生长的半导体区域的高度，因为可以执行两个或更多个外延生长步骤，其中外延生长掩模选择性地抑制在指定器件中形成半导体区域 地区。 在其他实施例中，公共外延生长工艺可以用于两个或更多个不同的器件区域，随后可以在所选择的器件区域上执行选择性氧化工艺，以便精确地降低所选区域中先前外延生长的半导体区域的高度 。

公开(公告)号：WO1996017376A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015260

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  PRAMANICK, Shekhar ,  LUNING, Scott ,  FEWKES, Jonathan

IPC: H01L21/027

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/32137

Abstract: A structure for patterning a polysilicon layer includes a TiN layer located above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is located above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

Abstract translation: 用于图案化多晶硅层的结构包括位于形成TiN / a-Si叠层的非晶硅（a-Si）层之上的TiN层。 TiN / a-Si堆叠位于多晶硅层的上方。 TiN层用作ARC以减少用于图案化多晶硅层的光致抗蚀剂的过度曝光，而a-Si层防止多晶硅层下面的层被污染。

公开(公告)号：WO2006132711A1

公开(公告)日：2006-12-14

申请号：PCT/US2006/014695

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  WAITE, Andrew, Michael ,  LUNING, Scott

Inventor： WAITE, Andrew, Michael ,  LUNING, Scott

IPC: H01L21/20 ,  H01L29/04 ,  H01L21/8238

CPC classification number: H01L29/045 ,  H01L21/76254 ,  H01L21/823807

Abstract: Methods for manufacturing an integrated circuit are provided. An exemplary method comprises the step of providing a silicon substrate (24) having a first crystalline orientation. A silicon layer (22) having a second crystalline orientation is bonded to the silicon substrate. The second crystalline orientation is different from the first crystalline orientation. The silicon layer is etched to expose a portion of the silicon substrate and an amorphous silicon layer (50) is deposited on the exposed portion. The amorphous silicon layer is transformed into a regrown crystalline silicon layer (52) having the first crystalline orientation. A first field effect transistor (80) is formed on the silicon layer and a second field effect transistor (82) is foπned on the regrown crystalline silicon layer.

Abstract translation: 提供了制造集成电路的方法。 一种示例性方法包括提供具有第一晶体取向的硅衬底（24）的步骤。 具有第二晶体取向的硅层（22）与硅衬底接合。 第二结晶取向与第一结晶取向不同。 蚀刻硅层以暴露硅衬底的一部分，并且在暴露部分上沉积非晶硅层（50）。 将非晶硅层转变成具有第一晶体取向的再生长晶体硅层（52）。 第一场效应晶体管（80）形成在硅层上，第二场效应晶体管（82）被覆在重新生长的晶体硅层上。

公开(公告)号：WO2006096380A1

公开(公告)日：2006-09-14

申请号：PCT/US2006/006936

申请日：2006-02-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  WAITE, Andrew, M. ,  LUNING, Scott

Inventor： WAITE, Andrew, M. ,  LUNING, Scott

IPC: H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/045 ,  H01L21/2007 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7833

Abstract: An integrated circuit and methods for its manufacture are provided. The integrated circuit (20) comprises a bulk silicon substrate (24) having a first region (64, 66) of (100) crystalline orientation and a second region (66, 64) of (110) crystalline orientation. A layer (62) of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor (96, 98) is formed in the layer (62) of silicon on insulator, at least one P-channel field effect transistor (90, 92) is formed in the second region (66, 64) of (110) crystalline orientation, and at least one N-channel field effect transistor (90, 92) is formed in the first region (64, 66) of (100) crystalline orientation.

Abstract translation: 提供集成电路及其制造方法。 集成电路（20）包括具有（100）晶体取向的第一区域（64,66）和（110）晶体取向的第二区域（66,64）的体硅衬底（24）。 绝缘体上的硅层（62）覆盖在体硅衬底的一部分上。 在绝缘体硅的层（62）中形成至少一个场效应晶体管（96,98），在第二区域（66,64）中形成至少一个P沟道场效应晶体管（90,92） （110）晶体取向，并且在（100）晶体取向的第一区域（64,66）中形成至少一个N沟道场效应晶体管（90,92）。

公开(公告)号：WO2004023533A3

公开(公告)日：2004-03-18

申请号：PCT/US2003/027366

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUNING, Scott ,  WIECZOREK, Karsten ,  KAMMLER, Thorsten

IPC: H01L21/336

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

公开(公告)号：WO1997036321A1

公开(公告)日：1997-10-02

申请号：PCT/US1996017407

申请日：1996-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GREENLAW, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L29/66575 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000 DEG C, and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000 DEG C heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed. The blocking layer on the gate stack need not be removed, which aids in minimizing substrate damage and in prevention of shorting a source-drain contact region to the substrate.

Abstract translation: 本发明涉及用于独立地掺杂半导体器件的栅极和源极 - 漏极区域的方法。 该方法通过提供具有隔离区域和薄绝缘层的衬底来启动。 在衬底上形成多晶硅层，其以第一掺杂级别掺杂有第一类型的掺杂剂。 在多晶硅层上形成能够承受1000℃温度的导电层材料，并且在导电层上形成阻挡层。 蚀刻多晶硅层，导电层和阻挡层以形成栅叠层。 源极 - 漏极区域随后以第二掺杂水平掺杂第二类型的掺杂剂。 源极 - 漏极区域在1000℃的热循环中被激活，随后在源极 - 漏极区域上形成TiSi 2。 然后形成接触。 栅堆叠上的阻挡层不需要去除，这有助于最小化衬底损伤并防止将源 - 漏接触区域短路到衬底。