公开(公告)号：WO2006022946A1

公开(公告)日：2006-03-02

申请号：PCT/US2005/018357

申请日：2005-05-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIRBELEIT, Frank ,  BURBACH, Gert ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred

Inventor： WIRBELEIT, Frank ,  BURBACH, Gert ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred

IPC: H01L23/544

CPC classification number: H01L22/34

Abstract: By providing a test structure (100) including a plurality of test pads (104), the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads (104) may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.

Abstract translation: 通过提供包括多个测试焊盘（104）的测试结构（100），可以以高效的方式确定应力和应变影响的电特性（例如电子迁移率）的各向异性行为。 此外，测试焊盘（104）可以以单个电路元件的数量级的空间分辨率来检测应力和应变诱发的修改。

公开(公告)号：WO2004061945A1

公开(公告)日：2004-07-22

申请号：PCT/US2003/035344

申请日：2003-11-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： VAN BENTUM, Ralf ,  KRUEGEL, Stephan ,  BURBACH, Gert

IPC: H01L21/762

CPC classification number: H01L21/76235 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76232

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches 206A, 206B, wherein a non-oxidizable mask 221 is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract translation: 在半导体器件的沟槽隔离结构中，在沟槽206A，206B内形成氧化物衬垫，其中在各种氧化步骤期间使用不可氧化掩模221，从而产生不同类型的衬里氧化物，从而形成不同类型的角圆化和 因此机械应力。 因此，对于指定类型的电路元件，可以调整相应的隔离沟槽的特性以实现最佳的器件性能。

公开(公告)号：WO2004021440A1

公开(公告)日：2004-03-11

申请号：PCT/US2003/027367

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  BURBACH, Gert ,  FEUDEL, Thomas

IPC: H01L27/06

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0805

Abstract: A semiconductor device comprises a field effect transistor (250) and a passive capacitor (240), wherein the dielectric layer (221a) of the capacitor (240) is comprised of a high-k material, whereas the gate insulation layer (231) of the field effect transistor (250) is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Abstract translation: 半导体器件包括场效应晶体管（250）和无源电容器（240），其中电容器（240）的电介质层（221a）由高k材料构成，而栅极绝缘层（231）由 场效应晶体管（250）由超薄氧化物层或氮氧化物层形成，以便在栅极绝缘层和下面的沟道区域之间的界面处提供优异的载流子迁移率。 由于电容器中的载流子迁移率不是很重要，所以高k材料允许提供每单位面积的高电容，同时具有足以有效减少泄漏电流的厚度。

公开(公告)号：EP1245045A1

公开(公告)日：2002-10-02

申请号：EP00952341.6

申请日：2000-07-31

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  BURBACH, Gert

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device comprising an insulating layer (108) which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer (108) of a metallization layer. In one embodiment, the porous layer (108) may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

公开(公告)号：EP1535332B1

公开(公告)日：2012-04-11

申请号：EP03791994.1

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  BURBACH, Gert ,  FEUDEL, Thomas

IPC: H01L27/06 ,  H01L27/08 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0805

Abstract: A semiconductor device comprises a field effect transistor (250) and a passive capacitor (240), wherein the dielectric layer (221a) of the capacitor (240) is comprised of a high-k material, whereas the gate insulation layer (231) of the field effect transistor (250) is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

公开(公告)号：EP1245045B1

公开(公告)日：2007-12-26

申请号：EP00952341.6

申请日：2000-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  BURBACH, Gert

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device comprising an insulating layer (108) which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer (108) of a metallization layer. In one embodiment, the porous layer (108) may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

公开(公告)号：EP1573801A1

公开(公告)日：2005-09-14

申请号：EP03768715.9

申请日：2003-11-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： VAN BENTUM, Ralf ,  KRUEGEL, Stephan ,  BURBACH, Gert

IPC: H01L21/762

CPC classification number: H01L21/76235 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76232

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches 206A, 206B, wherein a non-oxidizable mask 221 is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

公开(公告)号：EP1535332A1

公开(公告)日：2005-06-01

申请号：EP03791994.1

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  BURBACH, Gert ,  FEUDEL, Thomas

IPC: H01L27/06 ,  H01L27/08 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0805

Abstract: A semiconductor device comprises a field effect transistor (250) and a passive capacitor (240), wherein the dielectric layer (221a) of the capacitor (240) is comprised of a high-k material, whereas the gate insulation layer (231) of the field effect transistor (250) is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.